Server RAM vs desktop RAM: RDIMM, UDIMM and LRDIMM

Server RAM usually does not work in a desktop: most server memory is registered (RDIMM), a desktop takes only unbuffered (UDIMM), and on DDR4 the wrong type seats in the slot and the machine never starts. The two are the same 288-pin card with the notch in the same place, so nothing stops you and nothing tells you why. That is the most common expensive mistake in used memory buying, and it is exactly why server RAM looks so cheap: most people cannot use it. Two exceptions settle a lot of cases. ECC UDIMMs are sold as server memory but are unbuffered, and they are what entry servers, small NAS boxes, Xeon E workstations and ECC-capable Ryzen boards take. And DDR5 gave registered and unbuffered modules different notches, so on DDR5 the wrong type does not go in at all. The type letter on the label, the part number and the chip count tell you which kind a listing is before you buy.

The four types at a glance

Desktop and server memory comes in four kinds:

The difference between the rows is two kinds of chip. A registered module carries a registering clock driver (RCD) that re-drives the command and address signals to the memory chips; a load-reduced module adds data buffers on the data lines; an unbuffered module has neither. The machine has to configure the register before the module passes a single command, which is why the wrong type gives a dark screen rather than a slow machine (why the wrong type is a dead board). ECC is a separate property: it widens the module from 64 to 72 bits and adds no register, so an RDIMM is not “the ECC version” of a desktop module (ECC is a different axis).

Before you buy: four checks

Four checks, in this order, because each one is cheaper than the next.

1. What does the machine take? Not the board, the machine: processor plus board plus firmware. For a named server, the compatible machine index answers it directly; for a board, the manual’s memory support list; for a processor, RAM by processor. The answer is one of four words: unbuffered, unbuffered ECC, registered, load-reduced. The platform table covers the common cases.
2. What does the listing say the module is? Look for the type letter in the JEDEC label, the manufacturer part number, or the explicit word (how to read each). If the title stops at PC4-3200 and the photograph is a stock image, the type is unknown, and you should ask before buying rather than after.
3. Does the organization agree with the claimed type? 2Rx4 on a module described as unbuffered is a contradiction, and one of the two fields is wrong. Eighteen chips a side in the photograph is a registered module whatever the title says.
4. Does it fit the population you are building? The type settles whether the module works. The rank count, the capacity and the number of slots you fill settle its speed and whether the machine reaches the capacity you want: see ranks and 3DS and why your server won’t take its maximum RAM.

When the modules arrive, compare the capacity the machine reports with the capacity you paid for on the first boot, before the return window closes. A machine can post on part of what you installed and ignore the rest (what the failure looks like).

Which modules your machine takes

The memory controller has been inside the processor since Nehalem and Athlon 64, so the question is not what the board takes, it is what the processor and the firmware take together. An X58 board with a Core i7 in it accepts unbuffered memory only. The same board with a Xeon of the same era accepts registered memory, because the Xeon’s controller supports it and the board vendor shipped firmware that knows. Same slots, same traces, same BIOS image, different answer. The LGA2011 and LGA2011-3 generations behave the same way.

Five cases deserve emphasis.

The ECC UDIMM row catches people who assume “server memory” means registered. A Xeon E box, a small NAS, a Ryzen workstation with ECC enabled: all of them want unbuffered ECC, and an RDIMM will not work in any of them, though the seller’s title says “server” on both.

Threadripper changed sides, so it catches people in both directions. The 1000 to 3000 series on TR4 and sTRX4 (X399 and TRX40 boards) took unbuffered DDR4, ECC UDIMMs where the board supported them, and no RDIMMs. Threadripper PRO 3000WX and 5000WX on WRX80 moved to registered DDR4, and the 7000 and 9000 series on TRX50 and WRX90 take registered DDR5 only. Buying RDIMMs for an X399 or TRX40 board is the Ryzen mistake again. Buying UDIMMs for a TRX50 board is the same mistake in the other direction, made because the marketing calls Threadripper a desktop processor.

The LGA2011 rows are where the used market lives. Those boards accept both types, one at a time, which makes them the safest platform for a cheap high-memory machine. Check your board’s manual, though: consumer-branded X99 boards often support unbuffered memory only even though the processor would manage both.

The Xeon W-2100 and W-2200 workstations take registered ECC memory only. HP’s Z4 G4 QuickSpecs (Version 62, January 7, 2025) say “Only Registered DIMMs are supported,” Lenovo’s ThinkStation P520 PSREF (December 11, 2023) lists only DDR4 RDIMM ECC, and Dell’s Precision 5820 Tower Owner’s Manual (undated, checked October 15, 2026) lists ECC RDIMMs as “Supported only with Xeon W Series CPUs.” The caps in the table are Dell’s: 256 GB with a W-2100 (Skylake), 512 GB with a W-2200 (Cascade Lake). HP sells 64 GB RDIMMs only with a W-2200, which leaves a W-2100 at 8 x 32 GB. The same Dell and HP chassis were also sold with Core X processors (the HP ones on an X299 chipset), and those take non-ECC UDIMMs instead, so check the CPU in the listing first.

Apple appears more than once. The 2019 Mac Pro takes DDR4-2933 ECC RDIMMs and LRDIMMs. Before it, Apple lists the Mac Pro (Mid 2010) and (Mid 2012) as taking 1333 MHz DDR3 ECC UDIMMs and RDIMMs, one type at a time - a machine with both installed will not start - while the Early 2009 model takes ECC UDIMMs only. The Late 2013 model takes 1866 MHz DDR3 ECC, unbuffered or registered but not both at once, and holds up to 64 GB in four slots with RDIMMs; Apple says a mix of the two gives a memory error tone at power-on (Apple Support, “Mac Pro (Late 2013): Installing or replacing memory”, 101197, an archived article, checked October 15, 2026). Every Apple Silicon machine has its memory in the processor package and no slots at all.

For a named server, the memory by server index lists what each model takes, by vendor for Dell, HPE, Lenovo and Supermicro. For a laptop, or anything with soldered memory, how to check what RAM fits is the guide.

How to tell which type a module is

Sellers rarely make it obvious, and many do not know. Here is what settles it.

The JEDEC module label

JEDEC’s module label puts the type in the letter block after the speed grade, so a registered and a load-reduced module of the same grade are one letter apart: PC4-3200AA-R against PC4-3200AA-L. A DDR4 label reads left to right as generation, data rate, timing bin, then type:

PC4 - 3200 AA - R E2 - 12
 |      |    |   |  |
 |      |    |   |  +-- module design revision and other vendor fields
 |      |    |   +----- design revision
 |      |    +--------- MODULE TYPE - this is the letter you want
 |      +-------------- JEDEC timing bin
 +--------------------- generation: PC3 = DDR3, PC4 = DDR4, PC5 = DDR5

The timing bin is not the type and is regularly mistaken for it. It is a letter code for a JEDEC CL-tRCD-tRP triplet (AA is 22-22-22 at PC4-3200), and it reads the same on a registered and an unbuffered module of the same grade; what those numbers mean is in CAS latency explained. The type letters are the whole point:

DDR3 puts the letter straight onto the peak bandwidth figure instead of the transfer rate: PC3-12800R is a registered DDR3-1600 module, PC3L-12800R the 1.35 V version of the same thing, PC3-10600E an unbuffered ECC DDR3-1333 module. The conversion is peak MB/s = MT/s × 8, so 1600 × 8 = 12800.

Sellers routinely crop the title at PC4-3200, which is exactly where the information you needed was.

The manufacturer part number

This is the one that cannot be fudged, because the type is baked into the prefix or a fixed letter position, and a part number is copied off the label rather than typed from memory.

Micron’s DDR4 numbers are the most decodable. Take MTA36ASF4G72PZ-3G2:

MTA        Micron module
36         number of DRAM packages on the module
ASF        DDR4, 72-bit (ECC);  ATF would be DDR4, 64-bit (non-ECC)
4G72       organization: 4 Gigawords × 72 bits
PZ         registered;  LZ load-reduced, AZ unbuffered, HZ SODIMM
-3G2       DDR4-3200 speed grade

The organization field gives the capacity, counting data bits only: 4G × 64 bits ÷ 8 is 32 GB on the label, and the ECC devices you also paid for bring it to 36 GB physically present. The package count is a cross-check: 36 packages with x4 devices is 18 per rank and therefore two ranks, which is what 2Rx4 on the label will say.

Real parts to calibrate against: MTA36ASF8G72PZ-3G2 is a 64GB DDR4-3200 RDIMM, MTA72ASS16G72LZ-3G2 a 128GB LRDIMM, MTA18ASF4G72AZ-3G2 a 32GB ECC UDIMM, MTA16ATF2G64AZ-3G2 a 16GB non-ECC UDIMM and MTA8ATF2G64HZ-3G2 a 16GB SODIMM. M321R6GA0BB0-CQK is a 48GB DDR5-4800 RDIMM and M324R4GA3BB0-CQK a 32GB DDR5-4800 ECC UDIMM. SK hynix marks the type with a single letter, R, L or U, followed by 7 or 6 for the 72-bit and 64-bit split, so HMA84GR7AFR4N-UH is registered and HMA81GU6AFR8N-UH is unbuffered non-ECC. Micron changed prefix for DDR5, from MTA to MTC, and the field layout changed with it, so look the specific part up rather than carrying the DDR4 decode across. The rest of each maker’s scheme is decoded in buying used RAM on eBay.

OEM part numbers are a separate problem. Dell, HPE and Lenovo relabel modules with numbers that encode their own SKU, not the module type: a Dell SNP… number or an HPE …-B21 kit number tells you nothing about buffering until you look it up, and both vendors sell unbuffered ECC and registered parts under numbering schemes that look identical. The manufacturer part, usually printed on the same label in smaller type, is the one to read. An HPE server may log an iLO warning for non-HPE modules; they still work. The part number index lists current offers by manufacturer number.

SPD, the only definitive answer

Every module carries a small serial EEPROM holding a JEDEC-defined description of itself, and this is what the firmware actually reads. If you have the module in your hand, or the machine already runs, SPD ends the argument. The bytes that matter on DDR4, from the SPD annex of JESD21-C:

DDR3 uses the same byte 3 field with a slightly different value list, and puts LRDIMM at 0x0B. DDR5, specified by JESD400-5, keeps bytes 2 and 3 doing the same jobs and adds values for the clocked unbuffered types, but moves most of the rest of the map, so a DDR4 offset table will not decode a DDR5 module. Byte 3 is the field the firmware refuses on; everything else in this section is a proxy for it.

Reading it on a running Linux machine, in increasing order of detail:

sudo dmidecode -t memory
sudo modprobe ee1004 && sudo decode-dimms

dmidecode reads the firmware’s SMBIOS tables rather than the module, which is fine for the type and unreliable for anything the firmware chose not to fill in. A typical entry for a registered module:

Memory Device
	Locator: DIMM_A1
	Size: 32 GB
	Type: DDR4
	Type Detail: Registered (Buffered)
	Speed: 3200 MT/s
	Rank: 2
	Configured Memory Speed: 2933 MT/s

Type Detail says Registered (Buffered), Unbuffered (Unregistered) or LRDIMM, and that is the answer. Rank is the organization. And Configured Memory Speed differing from Speed is the population penalty made visible: the module is a 3200 part and the channel runs it at 2933, because of what else is installed or what the controller supports.

On Windows the same information comes out of SMBIOS through WMI, as a bitfield rather than a string:

Get-CimInstance Win32_PhysicalMemory |
  Select-Object BankLabel, Capacity, Speed, TypeDetail

TypeDetail is the SMBIOS memory-device type-detail word, and the values you will see are sums of its bits:

bit 7  = 128        Synchronous, set on essentially everything modern
bit 13 = 8192       Registered
bit 14 = 16384      Unbuffered
bit 15 = 32768      LRDIMM

8192 + 128  = 8320   → registered
16384 + 128 = 16512  → unbuffered
32768 + 128 = 32896  → load-reduced

16512 is the number on a desktop and 8320 is the number on a server. On the 2019 Mac Pro, system_profiler SPMemoryDataType reports the type alongside the part number.

The photograph

When the title is cropped and the seller has not answered, the picture is what is left, and it holds more than people expect.

Count the packages. A row of 8 or 16 means 64 data bits with x8 devices and therefore no ECC. A row of 9 or 18 means 72 bits and therefore ECC. Thirty-six packages, eighteen per side, means x4 devices and therefore, in practice, registered.

Look at the middle of the card. On a DDR3 or DDR4 registered module a chip sits in the electrical center, splitting the DRAM field into two halves, usually in a different package style from the DRAM around it. That is the RCD, and on DDR3 and DDR4 a chip in that position is close to conclusive.

Look at the row behind the connector. On a DDR4 LRDIMM there are nine small packages evenly spaced between the edge connector and the DRAM field. Those are the data buffers, and nothing else on a DDR4 module looks like that.

On DDR5 the center tells you nothing. Every DDR5 module, unbuffered included, has a PMIC in the middle with an inductor and a cluster of capacitors around it, plus an SPD hub and temperature sensors. Use the notch position instead, which on DDR5 settles it.

Heat spreaders hide all of this. A photograph of a module with a spreader on it is a photograph of a spreader.

The words in the title

“REG”, “Registered”, “RDIMM”, “LRDIMM” and “Buffered” all mean registered or load-reduced. Watch for “non-buffered”, which means unbuffered and is read as the opposite by nearly everyone who has just learned the word “buffered”.

What tells you nothing: the word “ECC” on its own, which is separate from buffering; “Server RAM”, which sellers apply to ECC UDIMMs as readily as to RDIMMs; “Dell”, “HPE” or “IBM”, which are chassis brands and appear on unbuffered ECC modules too; and the organization on its own, though it leans. 2Rx4, 4Rx4 and 8Rx4 are typical of registered server memory, because x4 devices are essentially absent from consumer modules. 1Rx8 and 2Rx8 appear on both and settle nothing.

Why the wrong type is a dead board and not a slow one

Memory is initialized in the earliest phase of firmware, before the display controller has been touched. There is no screen on which to print an error, so the failure shows up as a dark board with fans spinning, which looks exactly like a dead motherboard, a dead CPU or an unseated module. People return working boards over this. The sequence a host runs at power-on, and where a mismatch derails it:

1. Read the SPD. Byte 2 gives the DRAM generation and byte 3 the module type. If byte 3 names a type the platform’s memory code does not support, initialization stops here: the platform knows exactly what is wrong and has nowhere to tell you.
2. Apply power and reset the module. On DDR5 the module’s own PMIC has to be brought up over the sideband bus first, a code path that only exists on a DDR5-capable platform.
3. Program the registering clock driver. On a registered or load-reduced module the RCD’s control words have to be written: drive strengths, output enables, clock configuration, parity behavior, the operating speed band. The RCD comes out of reset in a state that does not forward commands. A desktop firmware has no code to write those words, because desktop modules have no register, so it skips the step and issues the first command into a module that is not listening.
4. Train the interface. Write leveling, read gate training, per-bit data deskew, on-die termination calibration, and on a load-reduced module the buffers’ own training. Training needs the DRAM to respond, and it does not.
5. Declare no usable memory. The slot is populated but cannot be trained, so as far as firmware is concerned it is empty.

The reverse mismatch, an unbuffered module in a registered-only platform, fails just as completely: the server firmware reads the SPD, sees a type its population rules do not permit, and refuses. Its timing model also expects the register’s one-clock offset, which an unbuffered module does not apply.

What the failure looks like from outside

On AMI firmware, which is most desktop boards and most Supermicro, the failure surfaces as a PEI status code you can only read from a POST-code display or a debug header:

0x50 is the wrong-buffering case stated explicitly. 0x55 is the one people actually see, because most boards with a Q-Code display show it while the DRAM debug LED stays lit: a module is present, the controller cannot train it, so firmware sees no memory. The matching AMI PEI beep code is a single beep for “memory not installed”.

The diagnostic LEDs are the cheapest instrument you have. Nearly every board built since about 2015 has four of them, labeled CPU, DRAM, VGA and BOOT, lit in sequence as each phase completes and left lit on the phase that failed. A DRAM LED that stays lit with a correctly seated module is a type or a training failure, not a contact problem, and reseating it for the fifth time will not change that.

The third outcome is the quiet one, and it costs more because you may not notice: the machine posts on what it can use and ignores the rest. Dell’s warning for its own servers is that a configuration breaking the population rules “might not boot, stop responding during memory configuration, or operate with reduced memory”.

The five-minute test before you conclude the board is dead

Strip the machine to one module in the first slot of the first channel, the slot the board’s manual says to populate first, and clear CMOS. If it posts, add modules back one at a time. If it does not post with a module the seller claims is the right type, put a module you know works in the same slot: if that posts, the problem is the module or its type, and if it does not, the problem is the slot or the CPU. Then check what actually got trained, not what the sticker says:

sudo dmidecode -t memory | grep -E "Size|Type:|Type Detail|Locator|Rank"

An entry reading Size: No Module Installed for a slot that physically contains a module is the tell, whether the cause is a wrong type, a dead rank or bent pins in the socket.

Mixing rules

The rule everyone breaks is about scope, not slots. Dell’s R750 manual states it most clearly: “Mixing of DDR4 DIMM types (RDIMM, LRDIMM, and 3DS LRDIMM), within channels, for Integrated Memory Controller (iMC), or across sockets are not supported.”

Buffering type is a decision for the whole machine, not per channel. You cannot put registered memory in one channel and unbuffered in another, split it by socket, or fill the empty slots of a registered machine with the unbuffered modules you already own. The choice between RDIMM and LRDIMM also changes a server’s maximum capacity by a large factor (why your server won’t take its maximum RAM).

Within a supported type, what you can mix depends on the machine, and one vendor’s machines disagree with each other. Dell’s Intel-based R750 says plainly that “x4 and x8 DRAM based memory modules can be mixed.” Its EPYC-based R7525 carves out an exception: an older 32GB RDIMM “with x4 data width and 8Gb DRAM density cannot be mixed with” a newer 32GB RDIMM “with x8 data width and 16Gb DRAM density in the same AMD EPYC processor unit.” Note the unit: gigabits of DRAM density, not gigabytes of module, so two modules identical on the label can make an unsupported pair. Follow the document for the machine in front of you.

The rules that hold everywhere:

• Populate the white slot in each channel first. Dell: “If only one DIMM is populated on a channel, then the DIMM should always be populated in the first slot in that channel (white slot).” White release tabs before black, always.
• Everything runs at the slowest module. Dell: “If memory modules with different speeds are installed, they operate at the speed of the slowest installed memory module(s).” Mixing a fast module into a slow machine wastes money.
• Capacity mixing is capped, and sometimes barred. The R750 permits two module capacities in a system and no more; the R7525 permits none. Speed bars it too: Dell’s 128GB LRDIMM at 2666 MT/s “cannot be mixed with” its 128GB LRDIMM at 3200.
• Balance the channels. A processor with eight memory channels and four modules installed runs at half its memory bandwidth however large the modules are, which costs far more real performance than the register’s latency.

Filling the second slot in each channel also costs speed regardless of type, as the R760 numbers show. For a used server build, fewer, larger modules beat more, smaller ones, right up until you run out of channels to fill.

What DDR5 changed

The common claim that DDR5 put a register on every module is wrong, and it leads people to buy the wrong thing. Four changes matter here.

The notch moved. JEDEC gave DDR5 UDIMMs and registered modules different notch positions, the first generation in which a server module physically cannot be pushed into a desktop board, or the reverse. Both are 288-pin cards that look alike at arm’s length. If you are buying DDR5 and get the type wrong, you find out at insertion rather than at power-on.

Power moved onto the module. Voltage regulation left the motherboard and became an on-module PMIC, alongside an SPD hub and one or two temperature sensors, on every DDR5 module class, unbuffered included. The module makes its own 1.1 V core supply and auxiliary rails from a raw rail the board delivers. Client modules take 5 V into that PMIC; RDIMMs and LRDIMMs take 12 V, and different rails plus different signaling are what forced the different key.

The channel split in two. A DDR5 DIMM is two independent 32-bit subchannels, each with its own command/address bus, 40 bits wide apiece on an ECC module. The DDR5 RCD serves both from one package, and the load-reduced specification pairs it with ten data buffers, five per subchannel, against DDR4’s nine. The rest of the generation change is in DDR4 vs DDR5.

Desktop modules got a clock driver, not a register. A client clock driver (CKD) regenerates the clock signal on the module, which produces the CUDIMM and CSODIMM form factors, published in 2024 as JESD323 and JESD324. JEDEC’s own figure for what it buys is a rise from 6400 to 7200 MT/s in the first version of the standard, with higher rates targeted later. The CKD re-drives the clock and nothing else: no command buffering, no effect on ECC, no server compatibility and no change to the key. A CUDIMM is a desktop module, and a board that supports CUDIMMs runs ordinary UDIMMs as well, usually with the clock driver bypassed.

Load-reduced memory effectively did not ship on DDR5

High capacity in DDR5 servers goes through 3DS RDIMMs instead. Dell’s PowerEdge R760 lists DDR5 RDIMMs only, from 1R 16GB through 8R 256GB, with no LRDIMM at any capacity, where the DDR4-era R750 lists RDIMM, LRDIMM and 3DS LRDIMM. The capacity formula shows why: with a 32 Gbit die and x4 organization, a two-rank RDIMM is already 128GB and a two-high stack 256GB, so the capacities that used to need data buffers are reachable without them. The buffer’s remaining argument was three modules per channel, and mainstream DDR5 server platforms are two.

If you are shopping DDR5 for a server, you are shopping RDIMMs, and an “LRDIMM” in a DDR5 listing title is usually a seller reusing a DDR4 template. The registered DDR5 listings are the place to start.

MRDIMM, the newest tier

MRDIMM - multiplexed rank DIMM, and Intel’s MCR DIMM is the same thing - adds a multiplexing RCD and multiplexing data buffers so two ranks are read simultaneously and interleaved onto the bus, delivering 128 bytes per access where a conventional DDR5 module delivers 64. JEDEC published it as JESD318. Gen1 runs at up to 8800 MT/s on Xeon 6900P and 8000 on the 6500P and 6700P, against 6400 for RDIMMs. It uses the same connector as DDR5 RDIMMs, so a board that takes MRDIMMs takes RDIMMs too, though not both at once, and support is confined to Intel’s Xeon 6 P-core parts and AMD’s sixth-generation EPYC. None of it is on the used market in any quantity; it is here so you recognize the acronym in a listing title.

ECC is a different axis entirely

The most common confusion in this subject is treating “registered” and “ECC” as one property. They are independent:

Nobody builds registered non-ECC, because anyone putting that much memory on a channel wants error correction. But “registered implies ECC” being true in practice does not make “ECC implies registered” true, and that inference is what puts RDIMMs in the shopping baskets of people with Ryzen boards.

ECC adds width: 64 data bits become 72, and on DDR5 each 32-bit subchannel gets 8 check bits, for 80. Every DDR5 device has on-die ECC, and on-die ECC is not system ECC: it corrects errors inside the chip and reports nothing to the host, so a 64-bit DDR5 UDIMM that a listing calls “ECC” is not an ECC module. The check is the width: 64 bits is not ECC, 72 or 80 is. The mechanism, the platforms that support it and how to prove correction is running are in ECC vs non-ECC.

How UDIMM, RDIMM and LRDIMM differ inside

This is the electrical reason the register exists, and what it costs. The three classes as circuits:

The command bus is the whole story

Two signal groups matter. The data lines (DQ) are trained one by one: the controller sweeps delay lines on each until it finds the center of the data eye, so a trace 3 mm longer than its neighbor costs nothing. The command and address lines (CA), and the clock with them, are broadcast: one command goes to every DRAM device on the selected rank at the same instant, with no per-device deskew on DDR4, so every device has to sample the same edge correctly at once.

A DQ line touches one DRAM device per rank, because a x8 device owns eight of the sixty-four lines and a x4 device owns four. A CA line touches every device on the module, on every rank: a multi-drop net with a dozen to several dozen stubs that all have to settle within one bus clock, at a controller that cannot compensate for any of them individually. Count it out for one DDR4 channel:

unbuffered, two 2Rx8 non-ECC modules in one channel
  64 data bits ÷ 8-bit chips  = 8 DRAMs per rank
  8 × 2 ranks × 2 modules     = 32 loads on the command/address bus
  each DQ net                 = 1 chip per rank × 4 ranks = 4 loads

unbuffered ECC, two 2Rx8 ECC modules in one channel
  72 data bits ÷ 8-bit chips  = 9 DRAMs per rank
  9 × 2 ranks × 2 modules     = 36 loads on the command/address bus

registered, two 2Rx4 ECC modules in one channel
  72 data bits ÷ 4-bit chips  = 18 DRAMs per rank
  18 × 2 ranks × 2 modules    = 72 DRAMs behind the registers
  the controller drives                 2 loads - one per module
  each DQ net                 = 1 chip per rank × 4 ranks = 4 loads, unchanged

The last line is the one people miss: an RDIMM does not reduce data-bus loading at all. The register is a command-bus device only. You cannot train away a multi-drop bus with thirty-six stubs on it, so the fix is a chip on the module that terminates the bus and starts a fresh, short one on the far side.

UDIMM: the address bus lands on every chip

An unbuffered DIMM is a passive card: nothing active between the edge connector and the DRAM except, on later generations, power management and the SPD EEPROM. That is the cheapest arrangement and what every consumer platform expects, and its ceiling has three causes: 32 loads on a full dual-rank, two-module channel with one 0.625 ns window per command at DDR4-3200; devices at the ends of the chain seeing the edge later than those in the middle; and consumer controllers that budget two chip selects per slot (JEDEC defines no four-rank unbuffered module for the client form factor). Together they give the practical rule: two modules per channel, two ranks each, and a speed bin lower than the same parts would run at one module per channel. Every desktop memory qualification list is that rule with specific numbers attached.

Capacity follows the die. Two ranks of eight x8 chips on the densest mainstream DDR4 die, 16 Gbit, make 32GB, and there is no 64GB DDR4 UDIMM because there is no double-density DDR4 die in volume and no client controller that will address four ranks. Everything in DDR4 above 32GB per module is registered, load-reduced or die-stacked. DDR5’s 24 Gbit and 32 Gbit dies make the 48GB and 64GB DDR5 UDIMMs by the same arithmetic. High capacity does not imply a register; it implies density, and a register only becomes necessary when you want high capacity and many modules on one channel at once.

ECC UDIMM is the same passive design 72 bits wide: nine x8 devices per rank instead of eight, the ninth carrying the check bits. Electrically it is a desktop module with no register.

RDIMM: the register, and the clock it costs

The registering clock driver sits in the electrical center of the module. It receives the command/address bus and the clock from the edge connector, terminates them, latches each command on a clock edge and re-drives fresh local copies to the DRAM. JEDEC defines the DDR4 part in JESD82-31, the data buffer that joins it on load-reduced modules in JESD82-32, and the SDRAM they talk to in JESD79-4.

The controller sees one CA load per module, whatever is on it: thirty-six DRAM packages, seventy-two dies, eight logical ranks, and the host-side bus still ends at one RCD input. That is what makes a 3DS RDIMM possible at all, and it is why ranks per channel are capped by the controller’s chip-select budget rather than by signal integrity. On the far side, the DDR4 RCD drives two independent output copies, each serving half the card, which is most of why registered modules reach speed grades an unbuffered card cannot at two modules per channel.

The cost is a clock. The RCD latches on one rising edge and drives out on the next, so every command arrives one bus clock late:

DDR3-1333: bus clock  666.7 MHz → tCK = 1.500 ns   → +1.500 ns per command
DDR3-1600: bus clock  800.0 MHz → tCK = 1.250 ns   → +1.250 ns per command
DDR4-2133: bus clock 1066.7 MHz → tCK = 0.938 ns   → +0.938 ns per command
DDR4-2400: bus clock 1200.0 MHz → tCK = 0.833 ns   → +0.833 ns per command
DDR4-2666: bus clock 1333.3 MHz → tCK = 0.750 ns   → +0.750 ns per command
DDR4-3200: bus clock 1600.0 MHz → tCK = 0.625 ns   → +0.625 ns per command
DDR5-4800: bus clock 2400.0 MHz → tCK = 0.417 ns   → +0.417 ns per command
DDR5-6400: bus clock 3200.0 MHz → tCK = 0.313 ns   → +0.313 ns per command

Those are conversions: the bus clock is half the transfer rate, and tCK is its reciprocal. The faster the memory, the cheaper the register: a DDR3-1333 RDIMM paid 1.5 ns for it, and a DDR5-6400 RDIMM pays 0.313 ns. At the JEDEC CL22 bin for DDR4-3200:

tCL   = 22 cycles × 0.625 ns          = 13.750 ns
+ RCD =  1 cycle  × 0.625 ns          =  0.625 ns
total                                 = 14.375 ns
increase on CAS latency               =  4.5 percent

A program waits on loaded round-trip latency, though, which on a two-socket server is usually somewhere between 80 and 100 ns once the cache hierarchy, the mesh or fabric hop, the controller queue and the DRAM access are counted. Against 90 ns:

0.625 ns ÷ 90 ns = 0.69 percent

Under one percent of the latency a workload actually sees, in exchange for being able to put four times as much memory on the channel. The 90 ns is an assumption that varies by platform, so read the exact figure as illustrative and the order of magnitude as solid.

Registered memory beats an unbuffered channel in gear-down

When a controller cannot meet command timing on a loaded unbuffered channel, it slows the command bus down. JESD79-4 defines a gear-down mode in which the command/address bus is sampled at half the clock rate, and older platforms do the same with 2N command timing, holding every command on the bus for two clocks. At DDR4-3200:

1N command timing: one command issued per 0.625 ns bus clock
2N command timing: one command issued per 1.250 ns
average added latency on a command   = 0.625 ns
command bus throughput               = halved

The unbuffered channel’s fallback costs the same latency as the register and halves command bandwidth on top of it. On a channel dense enough to force gear-down, the registered module is faster on the command bus.

The register is not in the data path, since read data goes from the DRAM to the edge connector without passing through anything, and it has nothing to do with ECC. On DDR4 it also checks command/address parity, which JESD79-4 defines with an ALERT_n line back to the controller: a CA bus error that would be an undetected wrong command on an unbuffered channel is blocked and retried on a registered one.

LRDIMM: buffering the data as well

An RDIMM fixes the command bus and leaves the data bus as it found it, which is fine until you want more than two ranks per module or more than two modules per channel. A load-reduced DIMM puts buffers on the data lines too, so the controller sees one DQ load per module no matter how many ranks are behind it.

DDR3 used one large central buffer, with every data line routed up to it over host-side traces on the order of 70 mm, which is part of why DDR3 LRDIMM had a bad reputation that DDR4 LRDIMM did not deserve. DDR4 replaced it with nine distributed data buffers in a row behind the edge connector, one per byte lane including the ECC lane, with host-side traces of roughly 8 mm. Propagation delay through a DDR4 data buffer is quoted as 1.67 ns + tCK/4, against 2.5 ns + tCK/4 for the DDR3 buffer:

DDR4-3200 data buffer:  1.67 + (0.625 ÷ 4)  = 1.67 + 0.156  = 1.826 ns
DDR3-1600 memory buffer: 2.5 + (1.250 ÷ 4)  = 2.50 + 0.313  = 2.813 ns

ratio 1.826 ÷ 2.813 = 0.649, so the DDR4 buffer is about 35 percent faster

The delay is paid outbound and inbound, so a read through a DDR4 data buffer costs about 3.65 ns of round trip, about four percent against the same 90 ns. That is the honest cost of load-reduced memory: roughly one percent of loaded latency for the register, and roughly four on top of that for the data buffers. It does not cost a speed bin: Micron’s 64GB DDR4 RDIMM MTA36ASF8G72PZ-3G2 and its 128GB LRDIMM MTA72ASS16G72LZ-3G2 carry the same -3G2 grade, DDR4-3200.

Each buffer has a host side and a DRAM side, and JESD82-32 defines a full training sequence for each face. That is why an LRDIMM takes visibly longer to train at power-on than an RDIMM of the same capacity, and why a fully populated load-reduced server can sit with a dark screen for a minute or more before it posts. DDR3 LRDIMMs also presented eight physical ranks to the controller as two or four, which made them fussy; DDR4 got its capacity from denser dies and 3DS stacking, which ranks and 3DS covers.

Three modules per channel is where load-reduced memory earns its price, and it is largely history: DDR3 servers and the DDR4 Xeon E5 v3 and v4 generation offered three slots per channel, but from Xeon Scalable’s first generation onward Intel’s mainstream server platforms have two, and AMD’s EPYC platforms have had two throughout. Going from one module per channel to three, a registered channel drops two speed grades and a load-reduced channel drops one, though the bins themselves are platform-specific.

FB-DIMM, from the DDR2-era Xeon 5000/5100 servers and Sun’s UltraSPARC T2 machines, daisy-chained modules through an Advanced Memory Buffer on each, and unlike everything since it was notched differently from an ordinary DDR2 DIMM: same 240 pins, neither mechanically nor electrically compatible. If you are buying DDR2 for an old workstation, that notch is on your side.

Why server modules hold more: one formula

Almost every “biggest module I can buy” question is four numbers multiplied together. The formula is derived from the module geometry rather than published by a vendor, and it reproduces the shipping catalog of every generation:

module capacity (GB) = (die density in Gbit ÷ 8)
                     × (64 ÷ DRAM device width)
                     × package ranks
                     × dies per package

The 64 is deliberate: marketed capacity counts data bits only, so the ECC chips do not appear in the number on the label even though you pay for them. Worked through the parts that exist:

DDR3 UDIMM,  4 Gbit x8, 2 ranks      0.5 × 8  × 2 × 1  =   8 GB
DDR3 UDIMM,  8 Gbit x8, 2 ranks      1.0 × 8  × 2 × 1  =  16 GB   (rare, late)
DDR3 RDIMM,  4 Gbit x4, 4 ranks      0.5 × 16 × 4 × 1  =  32 GB
DDR3 LRDIMM, 4 Gbit x4, 8 ranks      0.5 × 16 × 8 × 1  =  64 GB

DDR4 UDIMM, 16 Gbit x8, 2 ranks      2.0 × 8  × 2 × 1  =  32 GB
DDR4 RDIMM, 16 Gbit x4, 2 ranks      2.0 × 16 × 2 × 1  =  64 GB
DDR4 LRDIMM,16 Gbit x4, 2 ranks 2H   2.0 × 16 × 2 × 2  = 128 GB
DDR4 3DS,   16 Gbit x4, 2 ranks 4H   2.0 × 16 × 2 × 4  = 256 GB

DDR5 UDIMM, 24 Gbit x8, 2 ranks      3.0 × 8  × 2 × 1  =  48 GB
DDR5 UDIMM, 32 Gbit x8, 2 ranks      4.0 × 8  × 2 × 1  =  64 GB
DDR5 RDIMM, 32 Gbit x4, 2 ranks      4.0 × 16 × 2 × 1  = 128 GB
DDR5 3DS,   32 Gbit x4, 2 ranks 2H   4.0 × 16 × 2 × 2  = 256 GB

Every row is a module you can find on the used market except the last two, which are current-generation parts. The module type enters through only two of the four numbers: whether the devices are x4, and whether more than two ranks are permitted. A registered module holds four times what an unbuffered one does on the same die because x4 devices double the devices per rank and stacked packages double it again. And x4 is not a free choice: a 72-bit rank of x4 devices is eighteen packages, thirty-six on a dual-rank module, far too many to drive as a multi-drop command bus. The register is what makes x4 buildable.

The practical ceilings by type and generation:

The DDR2 and DDR3 rows are what you will meet on the used market, and they are where the gap hurts most. A DDR3 desktop board with four slots tops out at 32GB with the common 8GB modules. A DDR3 server board with eighteen slots and 32GB RDIMMs reaches 576GB: same generation, same dies, an eighteen-fold difference, and the whole difference is the chip in the middle of the card.

Speed comes from the population, not the type

A module type does not have a speed limit; a channel population does, and the type changes how fast it degrades. JESD79-4 tops the DDR4 bin list at 3200 MT/s. JESD79-5 defines DDR5 bins in steps of 400 MT/s from 3200 upward; 4800 was the lowest grade to ship in volume, and later revisions extended the list to 8800 MT/s. Anything above those numbers on a retail box is an XMP or EXPO overclock profile, which no server platform will honor.

Dell’s published population tables for the PowerEdge R760 make the shape concrete. DDR5-4800 RDIMMs run at 4800 at one module per channel and 4400 at two. So do the 5600 and 6400 parts: at two modules per channel they all land on 4400, so the faster modules buy you nothing in a fully populated machine. That is one vendor’s number for one machine, but the lesson generalizes: population beats grade, through load on the command bus (which the register removes), load on the data bus (which the data buffer removes) and the rank count on the channel.

On used DDR4, a registered channel at 1DPC runs its rated grade; at 2DPC it drops a bin or lands on the platform’s 2DPC number; at 3DPC, where the platform offers it at all, it drops hard. If you are filling a DDR4 server to its slot count, buy for capacity and ignore the speed grade, because the platform is about to overrule it. What the MT/s number means is in RAM speed: MHz vs MT/s.

Power and heat

Module power is dominated by the DRAM devices, not by the logic. The supply rails by generation, from the JEDEC device standards:

The type shows up in device count. A 2Rx4 RDIMM carries 36 DRAM packages plus an RCD, a 2Rx8 ECC UDIMM on the same die 18 packages and nothing else, and each package draws standby and refresh current whether or not it is being accessed. Nine DDR4 data buffers add more, which is why LRDIMMs idle warmer than RDIMMs of the same capacity. Server DIMMs are typically bare boards because the chassis pushes a great deal of air across them. In a quiet tower with two slow fans the buffers and the DDR5 PMIC run hot, and the module’s own temperature sensor asks the controller for a higher refresh rate, which costs bandwidth.

What the type does to price per gigabyte

New, the ordering follows the bill of materials: an ECC UDIMM adds a device per rank to a non-ECC one, an RDIMM adds a register and doubles the device count by going to x4, and a load-reduced or 3DS module adds nine more chips or a stacked package. Used, the ordering often inverts, for a reason that has nothing to do with what the modules cost to build.

Registered memory is retired in fleets. A data center refresh releases every module in a rack at once, on a schedule set by depreciation rather than by failure, usually in a condition indistinguishable from new because memory has no wear mechanism. Meanwhile the only buyers who can use a registered module are people who own a machine that takes one. Heavy supply meeting narrow demand produces the central fact of this market: on a like-for-like basis, used registered ECC memory is usually the cheapest memory per gigabyte you can buy, and it is not close. Unbuffered memory goes the other way: it is retired one desktop at a time, and everybody with a computer is a potential buyer.

The site’s price ranking sorts every listed module by price per gigabyte, and each buffering type has a page of its own: registered DDR4 against unbuffered DDR4 is the comparison to run, and registered DDR3 is where the gap is widest, because DDR3 servers have been leaving service for years and DDR3 desktops are still in use. Prices and counts move daily on Trends, so this guide quotes none of them; what counts as a price is set out in the methodology. Where prices are heading is a separate question, taken up in buy RAM now or wait.

Where the inversion inverts again

The fixed cost of receiving anything at all. Every module carries a floor cost of postage, packaging and handling. Call it F:

price per GB = (module price + F) ÷ capacity in GB

The F ÷ capacity term dominates at the bottom of the range. At a floor of 5 in any currency:

 4 GB module:  5 ÷ 4   = 1.25 per GB of pure logistics
 8 GB module:  5 ÷ 8   = 0.63
16 GB module:  5 ÷ 16  = 0.31
32 GB module:  5 ÷ 32  = 0.16
64 GB module:  5 ÷ 64  = 0.08

F varies by seller; the shape is the point. A 4GB module carries roughly sixteen times as much shipping cost per gigabyte as a 64GB one, which is why the smallest modules in every generation look poor value even when they are nearly free, and why buying four 8GB modules to reach 32GB is usually worse than buying one 32GB module, even before you count the three slots they take.

The top capacity in a generation is still in service in data centers, so it has not been retired in quantity, and its price per gigabyte sits above the capacity below it. The used sweet spot is one or two steps below the ceiling: on DDR4 that has been the 32GB and 64GB registered modules rather than the 128GB load-reduced ones, and on DDR3 the 16GB registered modules rather than the 32GB. Check the ranking, because the sweet spot moves as each capacity tier finishes leaving service.

The speed grade is nearly free on used server memory, because everything runs at the platform’s number anyway. A premium for a DDR4-2666 module over a DDR4-2400 one in a machine that tops out at 2400 buys nothing, and neither does 3200 in a 2933 machine. Buy the grade your platform runs and spend the difference on capacity.

Four things that are widely believed and are not true

“Registered RAM is slower.” One bus clock on the command path, 0.625 ns at DDR4-3200, under one percent of loaded latency, and an unbuffered channel pushed into gear-down or 2N timing pays the same and halves its command bandwidth.

“ECC memory means server memory means registered.” Three different properties, joined in the marketing and separate in the hardware. Unbuffered ECC goes in exactly the machines people most often try to put RDIMMs into.

“There is an adapter.” There is not, in either direction, for any generation: the mismatch is a chip the host has to configure, not a pin mapping. Anything sold as a DIMM adapter is a DDR2-to-DDR3 style scam, a riser that changes the mechanical position without changing a single signal, or a test fixture.

“It will just run slower, or with less memory.” Sometimes it does, and that is the expensive outcome rather than the lucky one: a machine that posts on part of what you installed costs you the return window if you do not notice. Everything in buying used RAM on eBay assumes the type is already settled.