RAM running slower than rated? MHz vs MT/s, XMP/EXPO and nine causes

A DDR4-3200 module does not run at 3200 MHz: 3200 is its data rate in MT/s on a 1600 MHz bus clock, and when memory reports less than its sticker, the usual cause is an XMP or EXPO profile that was never switched on. A tool that shows a true frequency, such as CPU-Z, reads 1600 MHz on a healthy DDR4-3200 kit, and the DRAM array behind that bus is cycling at 400 MHz. Memory that underperforms its rating has one of nine causes: six lower the speed the machine trains to (the profile is off, the processor is rated lower, too many modules or ranks share a channel, the modules do not match, the slots are wrong, or training failed and fell back), and three leave the speed reading alone (an empty channel, a memory controller that dropped to a slower gear, or hot memory). Each has a test, and several have no fix except different memory.

Nine reasons RAM runs slower than rated, and the test for each

The last three leave the configured speed alone, which makes them the hardest to find. Reading the speed shows where each number lives.

1. The profile was never enabled. The most common cause by a wide margin. The module is doing exactly what the JEDEC region of its SPD says, which is what firmware reads by default, for the reason the SPD section sets out. Enabling XMP or EXPO is not the same as it having worked, so read the speed back after.

2. The processor does not support that rate. A DDR5-6000 kit in a machine rated for DDR5-5600 will boot at a JEDEC bin and may or may not hold 6000 with a profile enabled. This is not a defect and the module is not faulty.

3. Too many ranks on the channel. Count modules, read the rank field from dmidecode -t 17, and look up the platform’s table in the population section. Four modules on a two-channel board is the classic. This is the expensive one to discover after buying, because the fix is different memory.

4. Mismatched modules. When the SPDs differ, the controller trains everything to a profile all of them support, which in practice means the slowest module’s JEDEC speed rather than anybody’s overclocking profile. A fast module added to a slower machine runs at the slower speed and says nothing about it, and the modules that had a profile have given it up.

5. The right count of modules in the wrong slots. Two modules on a four-slot board belong in the second slot of each channel, usually labeled A2 and B2, because the far slot terminates the channel better than the near one. The symptom is a machine that will not train at the rated speed and trains fine one slot over.

6. Training failed quietly and firmware reverted. The symptom is identical to case 1 and the cause is different: the profile is enabled and did not take. Compare the configured speed with the setting you believe is active after every firmware or module change, as boot-time training explains.

7. Not all channels are populated. Read the Locator values against the board manual rather than guessing from physical position. The symptom is normal speed and bandwidth cut in proportion to the empty channels (half, on a two-channel desktop with one module), which no speed field reports.

8. The controller fell back to a wider ratio. The configured speed is what you asked for and performance is worse than the grade below. Nothing in the operating system shows this; the firmware screen does. Setting the lower speed that holds 1:1 is a rare case of buying less and getting more, as gear modes explains.

9. The machine is hot. Above 85 degrees the refresh interval halves and takes about 14 percent of the channel with it on 16 Gbit dies, by the refresh arithmetic. Read the module’s thermal sensor, where one is fitted, with sensors on Linux or a monitoring utility on Windows. Registered server modules expect airflow and desktop cases frequently do not provide it.

No entry is “the module has degraded”, because memory does not wear. There is no counter to read and no endurance budget. A module either passes training at a speed or it does not, on its first day and its ten-thousandth. That is the central argument of buying used RAM on eBay, and it is why the speed field on a used listing is worth as much as on a new one.

Reading the speed a machine is actually running

Linux

dmidecode prints what firmware recorded for each slot. For a 16 GB DDR4-2666 registered module in a two-socket server holding two modules per channel, the output has this shape (an illustration, not a capture from a particular machine):

$ sudo dmidecode -t 17
Memory Device
	Array Handle: 0x1000
	Size: 16 GB
	Form Factor: DIMM
	Locator: DIMM_A1
	Type: DDR4
	Type Detail: Synchronous Registered (Buffered)
	Speed: 2667 MT/s
	Manufacturer: Samsung
	Part Number: M393A2K43CB2-CTD
	Rank: 2
	Configured Memory Speed: 2400 MT/s
	Minimum Voltage: 1.2 V
	Maximum Voltage: 1.2 V
	Configured Voltage: 1.2 V

Speed is what the module is rated for. Configured Memory Speed is what it is running at. A gap between them is your entire answer. Here a Samsung M393A2K43CB2-CTD, a DDR4-2666 registered part, is shown running at 2400, the kind of step down a platform’s table imposes at two modules per channel.

Both fields come from the SMBIOS Type 17 structure and both are in megatransfers per second. Older dmidecode builds label them Clock Speed and Configured Clock Speed in MHz; the value was always a transfer rate. The true DDR4-2666 bin is 2666⅔ MT/s and SMBIOS reports an integer, so 2667 is not a different speed from 2666.

Windows

Get-CimInstance Win32_PhysicalMemory |
  Select-Object BankLabel, PartNumber, Capacity, Speed, ConfiguredClockSpeed, ConfiguredVoltage

Speed and ConfiguredClockSpeed map onto the same two SMBIOS fields. Windows kept the misleading property name and documents the units as MHz. Read ConfiguredClockSpeed as MT/s regardless, because that is what firmware wrote into the structure the property is read from.

On an Intel Mac, system_profiler SPMemoryDataType reports per-slot speed. Apple Silicon has no memory slots, so nothing here applies to it.

Which number each tool shows

Windows 11 switched Task Manager from MHz to MT/s in Insider build 22635.3570, roughly a quarter-century late. dmidecode has reported MT/s for years. CPU-Z’s “DRAM Frequency” field is a genuine frequency: it reads 1600.0 MHz on a DDR4-3200 kit, and it is correct.

The section on buffered modules explains the MRDIMM row.

Reading the SPD, and what no tool shows

To see what the module itself claims rather than what firmware decided, read its presence-detect chip:

$ sudo modprobe ee1004
$ sudo decode-dimms | grep -E 'Part Number|Maximum module speed|Manufacturer'

That gives the module’s own JEDEC ceiling, which is how you tell “the module cannot go faster” from “the machine is not asking it to”. DDR5 needs newer tooling that speaks to the module’s hub device.

There is no standard interface for the controller ratio. SMBIOS carries no gear mode or UCLK:MCLK ratio, and nothing under /sys exposes one. The same goes for sub-timings beyond the four primaries, for whether a profile is applied rather than merely present, and for whether the last boot retrained. For those, the firmware setup screen is the instrument.

What to do on a listing page

1. Read the MT/s figure and ignore the unit. Every “3200MHz” in a listing title is 3200 MT/s on a 1600 MHz bus. The unit is wrong everywhere, including on manufacturers’ boxes; matching the number is what counts.

2. Check the generation prefix on any PC number first. PC3-12800 and PC4-12800 are the same bandwidth on modules that will not fit the same board.

3. Look up two numbers before you shop: what your processor supports, and what your board supports at the module count you intend. The lower of the two is the grade to buy. Start from the CPU pages for the first and the compatibility pages for the second.

4. Decide the module count before the module size. Two large modules beat four small ones on speed on every client platform; on a server the goal is to fill every channel. Both rules come out of the same population tables.

5. Do not pay for a grade the machine will downclock. A DDR4-2666 registered module in a platform validated at 2133 runs at 2133 and the premium is gone. Compare grades on the DDR4 server listings and buy the one your table says.

6. Match the set, or expect to lose the profile. A mixed set trains to the slowest module’s JEDEC bin, not anybody’s XMP or EXPO profile. Two separately bought kits of the same part number are not one kit.

7. Read the speed back after every change. Compare Speed with Configured Memory Speed. Firmware that silently reverted looks identical to firmware that was never configured.

8. On a desktop, prefer the grade that holds a 1:1 controller ratio over the highest grade you can afford. DDR5-6000 at 1:1 beats DDR5-6400 at 1:2 for anything latency-sensitive; the CAS time is identical in nanoseconds and the higher grade buys 6.7 percent of peak bandwidth.

9. Check the bin letter when two identical-looking listings differ in price. PC4-2666T and PC4-2666W are both PC4-21300, at CL17 and CL20: 12.75 ns against 15.0 ns to first word, which matters on a latency-bound workload and not at all on a streaming one.

10. Populate every channel before you add capacity. Eight modules in a twelve-channel server is 67 percent of the platform’s memory bandwidth for the life of the machine, and nothing will ever tell you so.

Why 3200MHz memory is 3200 MT/s on a 1600 MHz clock

PC100 and PC133 SDRAM, the generation before DDR, did one transfer per clock period, so MHz and transfers per second were the same number. DDR broke the equivalence in 2000 and the retail vocabulary never updated. This site’s speed pages, such as DDR4-3200, say MHz in their titles because that is what people search for; the field behind them stores MT/s.

Two doublings, and only one of them is the DDR in DDR

The factor between 1600 MHz and 3200 MT/s is double data rate: the I/O pins latch a bit on the rising edge of the clock and another on the falling edge.

The second doubling is bigger and almost never mentioned. DRAM cells are slow, and have been about as slow for twenty-five years, because a cell is a capacitor and a sense amplifier and the time to resolve its charge is set by physics that process shrinks do not improve. So the chip fetches a wide chunk internally on each access and shifts it out narrow and fast. That is prefetch, written 2n to 16n for the bits fetched per I/O pin per access. DDR4 uses 8n, serialized across four clock cycles; DDR5 uses 16n, across eight.

The array clock is the number nobody prints

Divide the bus clock by half the prefetch and you get the rate the array is actually being cycled at.

Across twenty-five years and five generations the DRAM array went from 200 MHz to 550 MHz, while the data rate went up by a factor of twenty-two. Everything else came from prefetching wider and clocking the interface harder.

At DDR5-6400 the array runs at exactly the rate a DDR4-3200 array does. DDR5 did not make DRAM faster; it made the serializer wider. The same fact explains why latency stood still: a DDR4-3200 module at its JEDEC CL22 bin takes 13.75 ns to first word, exactly what a DDR3-1600 module at CL11 took about a decade earlier. The CAS latency guide works through that.

What JEDEC writes down is a period, not a frequency

JESD79-4, the DDR4 standard, does not publish a clock frequency for its speed bins. It publishes tCK(avg), the average clock period, in nanoseconds, and every timing in the device is a multiple of that period.

DDR5 works the same way, and DDR4-3200 and DDR5-3200 have identical bus clocks. They differ in prefetch, bank count, subchannels and where the voltage regulator sits, not in how fast the interface is clocked.

The repeating decimals, and where 133⅓ came from

The PC front side bus settled on 66⅔ MHz, then 100 MHz, then 133⅓ MHz, which is 400 ÷ 3, and every generation since has inherited multiples of it.

133⅓ MHz × 2 (DDR) × 8 (multiplier)  = 2133⅓ MT/s   sold as DDR4-2133
133⅓ MHz × 2 × 10                    = 2666⅔ MT/s   sold as DDR4-2666
133⅓ MHz × 2 × 11                    = 2933⅓ MT/s   sold as DDR4-2933

So DDR4-2666 is genuinely 2666⅔ MT/s, and a machine reporting 2667 MT/s is rounding, not disagreeing with the label. DDR5 escaped the problem by defining its bins in steps of 400 MT/s from 3200 upward, which is why no DDR5 grade has a two-spelling problem the way DDR4-2933 does.

DDR5’s two subchannels are not extra channels

A DDR5 DIMM presents two independent 32-bit subchannels where DDR4 presents one 64-bit path, and Intel and AMD count those subchannels as channels, so a two-slot DDR5 desktop is described as four-channel. It is not wider: 4 × 32 bits is the same 128-bit data path as a two-slot DDR4 board’s 2 × 64, so all of DDR5’s bandwidth advantage there comes from the transfer rate. DDR4 against DDR5 covers what else changed.

Peak bandwidth, worked out

Everything here is multiplication. Where a figure is worked out here rather than published, it is this site’s arithmetic; the short sums are written out below and the longer ones are in the CAS latency guide. A 64-bit channel moves eight bytes per transfer.

bytes per second = transfers per second × width in bytes

DDR4-3200, one 64-bit channel
  3200 × 10^6 × 8 bytes  =  25,600 MB/s  =  25.6 GB/s

DDR5-6000, one DIMM (two 32-bit subchannels, 64 bits total)
  6000 × 10^6 × 8 bytes  =  48,000 MB/s  =  48.0 GB/s

Those MB/s are decimal, 10^6 bytes, which is where the PC number comes from. The full ladder:

ECC and ranks do not change these figures. A DDR4 ECC DIMM is 72 bits wide and a DDR5 ECC module 80, but the extra bits are check bits, so the payload and the bandwidth match a non-ECC module of the same grade; the ECC guide covers what they are for. A dual-rank module’s two ranks share the same 64 data pins and only one drives the bus at a time, so a 2Rx8 and a 1Rx8 module at the same grade have identical peak bandwidth; ranks and 3DS modules covers what the second rank does buy.

Real platforms multiply the channel figure out a long way, and a published memory bandwidth number on a CPU spec sheet is never a measurement. It is channels times rate times eight:

AMD EPYC 9004 "Genoa"     12 channels × DDR5-4800 × 8 B  = 460,800 MB/s = 460.8 GB/s
AMD EPYC 9005 "Turin"     12 × DDR5-6400 × 8             = 614,400 MB/s = 614.4 GB/s
Intel Xeon 4th gen        8  × DDR5-4800 × 8             = 307,200 MB/s = 307.2 GB/s
Intel Xeon 6, MRDIMM      12 × 8800 × 8                  = 844,800 MB/s = 844.8 GB/s
Intel Xeon E5-2600 v3     4  × DDR4-2133⅓ × 8            =  68,267 MB/s =  68.3 GB/s
Intel Xeon Scalable 2nd   6  × DDR4-2933⅓ × 8            = 140,800 MB/s = 140.8 GB/s

Divide by core count and the picture inverts: a 96-core EPYC 9004 has 460.8 ÷ 96 = 4.8 GB/s per core, about the same as a twelve-year-old fourteen-core Xeon E5-2697 v3 at 68.3 ÷ 14 = 4.9, and about two fifths of an 8-core desktop on two channels of DDR5-6000 at 96.0 ÷ 8 = 12.0.

PCn-nnnnn, and the rounding that is a habit

The PC number is the peak bandwidth in MB/s, rounded to something marketable. The generation digit is the part that matters.

The rounding is a habit, not a rule: DDR-266’s 2,133 became PC2100 by rounding down and DDR-333’s 2,667 became PC2700 by rounding up. Every “also” in the table is one grade sold under two spellings, DDR2’s PC2-4200, PC2-5300 and PC2-8500 included. DDR4-2933 is the live case: the arithmetic gives 23,466⅔, the grade appears as PC4-23400 on most listings and PC4-23466 on others, and neither is a JEDEC designation. Searching for one spelling and not the other is a genuine way to miss stock.

The label on a server module is a third number again

A registered module’s sticker says something close to PC4-2666V-RD1-11. That is JEDEC’s module nomenclature, it states the data rate directly, and the letter after the rate is a CAS latency bin, not a voltage and not a revision. The DDR4 bin letters, from the speed bin tables in JESD79-4:

The sequence skips I, O, Q, X and Z, which are confusable with digits on a small label. Four different parts share one marketplace number: PC4-2666T, U, V and W are all PC4-21300 and are CL17, CL18, CL19 and CL20. At DDR4-2666, CL17 is 12.75 ns and CL20 is 15.0 ns, a 17.6 percent difference in the time to first word and none in streaming bandwidth. Some DDR5 bins carry an N suffix for the 24 Gbit and 48 Gbit dies behind 48 GB and 96 GB modules, and Micron’s DDR5-5600 datasheets list AN, B, BN and C bins at 40-40-40, 46-45-45, 46-46-46 and 50-49-49, so read the CL off the listing rather than inferring it from the letter.

In RD1-11, the first letter is the useful one: R for registered, U for unbuffered, L for load-reduced, S for a small outline module. The rest is a JEDEC raw card reference, a PCB layout and not a speed field. Buying used RAM on eBay decodes the rest of a label and a part number.

The SPD decides what the machine boots at

Every module carries a small EEPROM, the serial presence detect chip. At power-on the memory controller reads it over a two-wire bus and learns what it is holding. Nothing about the speed of your memory is negotiated. It is looked up.

What is actually in there

For DDR4 the SPD is 512 bytes, defined by JESD21-C, Annex L: a base configuration of density, banks, rows, columns, width, rank count and timings, then manufacturing data and a region JEDEC leaves open. DDR4 stores times as a count of a medium timebase of 125 picoseconds, with a signed correction in a fine timebase of 1 picosecond. Byte 18 holds tCKAVGmin, the shortest clock period the module is qualified for, which is the whole speed rating of the module in two bytes:

DDR4-3200   tCK = 625 ps   625 ÷ 125 = 5 exactly        MTB 5,  FTB   0
DDR4-2666   tCK = 750 ps   750 ÷ 125 = 6 exactly        MTB 6,  FTB   0
DDR4-2400   tCK = 833 ps   833 ÷ 125 = 6.664            MTB 7,  FTB -42

JEDEC rounds up to the next 125 ps unit and subtracts the difference: a DDR4-2400 module carries 7 and minus 42, and 7 × 125 - 42 is 833.

DDR5 stores timings directly in picoseconds in a 1024-byte SPD defined in a JEDEC document of its own, behind a hub device on the module. On Linux that needs a driver that speaks to the hub, where DDR4 SPD is readable with the older ee1004 driver.

The controller takes a minimum over four things

The speed a machine trains to is the lowest of four numbers, and people routinely blame a downclock on the wrong one.

Nothing in that list is the number printed on a retail kit’s box. A DDR5-6000 kit’s JEDEC region commonly declares DDR5-4800 CL40, because that is a real JEDEC speed bin and DDR5-6000 is not one. The 6000 lives somewhere else.

The vendor region, where XMP and EXPO live

JEDEC leaves the last part of the SPD open, and the overclocking profiles sit there. On DDR4, XMP 2.0 occupies the final 128 bytes of the 512-byte SPD and holds two profiles. DDR5’s XMP 3.0 lives in the equivalent region of the larger SPD, holds more profiles, and made some of them writable so a board or a user can store a tuned set back onto the module. AMD’s EXPO is the same idea in a different vendor block, DDR5 only, with the profile contents published.

Firmware that reads only the JEDEC region is behaving correctly. It is not ignoring your kit. The kit put its headline speed in a region JEDEC does not define, and reading it is opt-in.

XMP and EXPO overclock the processor, not the module

This distinction is the difference between a warranty claim and a wasted afternoon. The module vendor tested its DRAM at the profile speed and sells the result as validated there, so for the DIMM the profile is a rating.

The memory controller is being overclocked, and it is inside the processor. Intel and AMD rate their controllers at specific JEDEC data rates. Running one at DDR5-7200 when the processor’s spec sheet says DDR5-5600 is operating part of the CPU outside the specification it was sold under. Buying a 7200-rated kit does not change what the controller in your particular chip can do.

The voltage is the tell

A DDR5 profile at 1.35 V is asking for 23 percent more than the standard operating voltage, which is 1.35 ÷ 1.1: an overclock by any definition, however normal and usually harmless.

DDR5 moved voltage regulation onto the module, in a power management IC, where DDR4 boards supplied the rails. The PMIC has a ceiling it will accept, and on many modules that ceiling is locked in a way a board cannot override. Server modules are generally locked and retail overclocking modules generally are not, which is why a server RDIMM will not do enthusiast voltages even in a board that would offer them.

A kit is binned as a set

A 2 × 16 GB kit was tested together, at its profile, on a reference platform. Two separately bought kits of the same part number were not. Four modules from two kits is an untested configuration even when every part number matches, and a four-module configuration is usually a lower speed grade whatever the profile says, as the population tables show. The profile was tuned for the electrical load of two modules, not four.

What the vendors say

Intel describes XMP as a form of memory overclocking and warns in its own support material that altering clock frequency or voltage may void warranties and reduce stability and life; AMD carries an equivalent disclaimer for memory overclocking including EXPO. This is not a hidden term. It is on the page that explains how to turn the feature on. The risk in practice is small. The point is that a memory profile is the one setting people enable without registering that they have overclocked anything.

The DDR5 clock driver, and the speeds that now require one

From 6400 MT/s upward, JEDEC’s DDR5 module specifications require an unbuffered module to carry a clock driver that regenerates the clock on the module. The form factors are named CUDIMM and CSODIMM. A board without clock driver support cannot run a CUDIMM at its rated speed; many such modules have a bypass mode that runs them as ordinary UDIMMs at a reduced rate, so the module posts, works and is slow, with nothing saying why. Check the board’s support list for CUDIMM before buying anything at DDR5-6400 or above.

Gear modes: the memory controller runs its own clock

This explains the result people find impossible: a higher grade of memory, correctly configured, running slower than the grade below it. The memory controller has its own clock, and its ratio to the memory clock is usually the single largest influence on latency in the whole memory path.

Intel’s gears

Intel calls the ratio Gear mode, and the number is the divisor applied to the controller.

Intel’s own platform documentation for the 12th generation lists no Gear 1 configuration with DDR5 at all. The DDR4 side of the same processor supports Gear 1 through DDR4-3200, which is why a 12th-generation DDR4 board could post latency figures a DDR5 board of the same generation could not touch, and why early DDR5 looked so unconvincing in latency-sensitive testing.

AMD’s UCLK, MCLK and FCLK

AMD exposes three clocks rather than a gear number.

On AM4 all three wanted to be coupled, and the well-known target was FCLK 1800 with DDR4-3600, everything at 1:1:1. On AM5, home of the Ryzen 7000 and Ryzen 9000 desktop processors, the fabric is decoupled, and the question is whether UCLK can hold 1:1 against MCLK.

AMD names DDR5-6000 as the recommended operating point for AM5 rather than as a maximum, and the reason is the ratio, not the DRAM. Above the point where the controller can hold 1:1, it falls back to 1:2, and the fall costs more than the extra transfers return for most workloads. AMD’s recommendation makes DDR5-6000 the grade to start from on AM5.

What the ratio costs

At DDR5-6000 with UCLK 1:1, the controller’s clock period is:

MCLK = 6000 ÷ 2 = 3000 MHz      period = 1 ÷ 3000 MHz = 0.3333 ns
UCLK at 1:1     = 3000 MHz      period = 0.3333 ns

At DDR5-6400 with UCLK 1:2:

MCLK = 6400 ÷ 2 = 3200 MHz      period = 0.3125 ns
UCLK at 1:2     = 1600 MHz      period = 0.6250 ns

The controller’s clock period nearly doubles, from 0.3333 ns to 0.6250 ns, an increase of 87.5 percent, while the data rate rises by 6.7 percent.

The cost in nanoseconds depends on how many controller clock periods a transaction spends inside the controller, a pipeline depth no vendor publishes. If the front end is ten stages deep, the added time is 10 × (0.625 - 0.3333) = 2.9 ns; if twenty, 5.8 ns. Those depths are assumptions. The direction is certain, the order of magnitude is a few nanoseconds, and the exact figure is not calculable from outside the company that designed it.

The cliff, stated as a comparison

The DRAM is exactly as fast in both columns. The entire trade is 6.7 percent more peak bandwidth against a controller running at half rate, and for anything latency-sensitive that is a losing trade. This is why a 6400 kit can benchmark below a 6000 kit in the same board.

Where the cliff stops mattering

Past the cliff the ground is flat, so enough extra speed eventually wins the bandwidth argument back even though the latency never recovers.

DDR5-6000 at 1:1      48.0 GB/s   CAS 30 × 0.3333 =  10.00 ns   UCLK period 0.3333 ns
DDR5-8000 at 1:2      64.0 GB/s   CAS 38 × 0.2500 =   9.50 ns   UCLK period 0.5000 ns

Thirty-three percent more peak bandwidth, a slightly better CAS time, and a controller still at half rate. For a workload that streams, DDR5-8000 at 1:2 is the better configuration; for a workload that chases pointers, DDR5-6000 at 1:1 usually still wins. For most desktop buyers the difference between the two is smaller than the price difference.

Past the platform’s 1:1 limit you are paying a premium per gigabyte for peak bandwidth and giving back latency. Below it you are buying both. The limit belongs to your particular chip, not to its model.

Population sets the speed, and the number is published before you buy

A correct module, correctly installed, in a machine that supports its grade, can still run slower for a reason that is not a fault. Every rank and every slot on a channel loads the bus, and past the point where termination and, on DDR5, equalization in the DRAM’s own receiver can compensate, the only lever left is to slow down. A platform’s population table is the speed at which the vendor will guarantee the signaling with that much load on the bus.

Intel’s desktop tables, and what they index on

Intel’s 12th generation DDR5 table is the instructive one, because its left column is not modules. It is slots:

The first two rows hold the same modules and the same ranks, 400 MT/s apart, and the only difference is whether the board has an empty second slot on each channel. An unpopulated slot costs speed: the branch in the wiring is there whether or not a module sits at the end of it, and an unterminated branch reflects. That is why a two-slot ITX board often supports a higher grade than the full-size board with the same chipset. The DDR4 side of the same generation agrees:

A dual-rank module in one slot holds DDR4-3200; two single-rank modules in two slots do not, at the same rank count on the channel. The second rank on one module is free here, and the second module costs 267 MT/s. The order is slots, then modules, then ranks. The tables are Intel’s data; the stub explanation is a reading of the signaling, not something Intel states.

AM5

AMD’s support table for AM5 drops from DDR5-5200 with two modules to DDR5-3600 with four, a 30.8 percent cut in peak bandwidth from a decision most people make on capacity alone. Four 16 GB modules and two 32 GB modules give the same 64 GB, and the 32 GB module’s second rank costs nothing here: AMD publishes 2x1R DDR5-5200 and 2x2R DDR5-5200 on a Ryzen 9 7950X’s own specification page.

2 × 32 GB at DDR5-5200    2 DIMMs × 5200 × 8 B = 83,200 MB/s = 83.2 GB/s
4 × 16 GB at DDR5-3600    4 DIMMs × 3600 × 8 B = 115,200 MB/s

                          but the data path is 128 bits either way,
                          so the honest comparison is per channel:
2 × 32 GB                 5200 × 8 × 2 = 83.2 GB/s
4 × 16 GB                 3600 × 8 × 2 = 57.6 GB/s

The second line is the one that matters and it is 31 percent less bandwidth. Four modules do not add channels on a two-channel board; they add ranks to the channels that exist. The pair of larger modules wins on speed and leaves two slots for later, though larger modules usually cost more per gigabyte.

Server platforms

Server vendors publish the same tables at more depth, because a server can have three slots per channel. These are the processor vendors’ figures:

Take the chassis vendor’s table over the processor vendor’s where they disagree, because the chassis vendor’s is the one that binds. A server board adds its own trace lengths, connectors and qualification program, and an HPE, Dell or Lenovo population guide is often more conservative than Intel’s or AMD’s figure for the same silicon. The machines on this site’s compatibility pages, a Dell PowerEdge R730 or an HPE ProLiant DL380 Gen9 among them, carry the chassis vendor’s figures.

Three modules per channel, on older platforms, is where the speed cost becomes the dominant fact:

Xeon E5-2600 v3, four channels, DDR4-2133 modules throughout

 4 modules, 1 per channel    4 × 2133⅓ × 8 = 68.3 GB/s    at DDR4-2133
 8 modules, 2 per channel    4 × 1866⅔ × 8 = 59.7 GB/s    at DDR4-1866
12 modules, 3 per channel    4 × 1600   × 8 = 51.2 GB/s   at DDR4-1600

Tripling the module count costs 25 percent of the peak bandwidth. Capacity usually justifies it, but it should be a decision rather than a surprise. Server memory capacity limits works the same tables from the capacity side.

Registered, load-reduced and MRDIMM modules at speed

Server RAM against desktop RAM covers which boards take which type; what matters here is what each buffer does to speed. A registered module’s registering clock driver re-drives the command, address and clock signals and does not touch the data bus, so every rank still loads the data bus and a second registered module per channel still costs speed. The register itself adds one clock period of command latency.

A load-reduced module adds buffers on the data path, nine on DDR4, so the host sees one data load per module however many ranks it carries, which is how 128 GB and 256 GB modules exist. On DDR3 and the earliest DDR4 platforms, load reduction bought a higher validated speed at high module counts; on most later DDR4 servers, registered and load-reduced modules get the same speed at two per channel, and the load-reduced module buys capacity, not rate. Stacked 3DS modules present one load and several logical ranks, so they do not cost a speed grade for their ranks; ranks and 3DS modules has the detail. Registered DDR5 has reached 8000 MT/s in shipping product, because the register already regenerates the clock and command bus.

MRDIMM breaks every definition of speed. A multiplexed rank module’s buffers interleave two ranks’ worth of data and present it to the host at double the DRAM’s rate, so a first-generation MRDIMM sold as DDR5-8800 contains DRAM running at 4400 MT/s. Intel’s Xeon 6 is the platform that takes them; AMD’s EPYC 9006 “Venice” takes the faster MRDIMM-12800, whose DRAM runs at 6400 MT/s.

MRDIMM-8800:  DRAM at 4400 MT/s, host interface at 8800 MT/s
              12 channels × 8800 × 8 B = 844.8 GB/s peak per socket

The bandwidth is real, the array clock is 275 MHz, and the latency is set by the 4400 MT/s devices plus the multiplexing.

Boot-time training is why speed is not simply a setting

Between reading the SPD and running at a speed there is a process that takes seconds on a desktop and minutes on a loaded server.

DDR3 introduced fly-by routing: the command, address and clock traces run past the devices in sequence instead of reaching all of them at once, so the clock arrives at the last device later than the first. Write leveling measures that skew per device and delays each one’s data to match. It has to be done at boot because it depends on the board, the module and the temperature. Around it sit the other calibrations:

Each runs per module, per rank and often per device, which is why the time scales with installed memory and a fully populated two-socket server can take several minutes to reach a display.

Firmware caches the trained values, keyed to the configuration that produced them. Change a module, move a module between slots, or change the speed setting, and the key misses and the machine retrains from scratch. That is why a machine that booted instantly yesterday can sit at a dark screen for minutes after new memory goes in, and not be broken.

Training can fail. Some boards stop and say so. Many retry at a lower speed, or with the JEDEC profile instead of the enabled overclocking profile, and boot normally without telling you anything. A machine reverted from an enabled 6000 profile to DDR5-4800 looks exactly like one never configured; reading the configured speed back after every firmware change is the only test.

Peak is a ceiling nothing reaches

The bandwidth arithmetic assumes every clock period carries data. None do, and the limits behind most of the shortfall are specified in the same standard as the speed bins.

Refresh, the activate window and the bank count

JESD79-4 sets DDR4’s refresh interval at 7.8 microseconds (7.8125 exactly) at or below 85 degrees, and on 16 Gbit dies each refresh occupies the device for 550 ns: 550 ÷ 7,812.5 is 7.0 percent of the channel’s time, which takes DDR4-3200 from 25.6 GB/s to 23.8 GB/s before a useful byte moves. Above 85 degrees the standard halves the interval to 3.9 microseconds and the cost doubles to 14.1 percent, and the module never says a word about it. That is the technical content of the advice to put airflow over server modules: the DRAM does not fail at 86 degrees, the refresh rate doubles and takes bandwidth with it.

Two more limits cap random access. tFAW allows no more than four row activations per rank in a rolling window, which, by this site’s arithmetic, caps a single-rank channel where every access opens a new row at between a third and two thirds of peak (4 × 64 B ÷ 30 ns is 8.5 GB/s and ÷ 15 ns is 17.1 GB/s, against DDR4-3200’s 25.6). tFAW is specified per rank, so a second rank doubles that ceiling, the real benefit of dual-rank memory and invisible in any peak figure. And a bank cannot reopen a row until its row cycle time has passed: by this site’s arithmetic, DDR4’s 16 banks reach 87 percent of peak in the worst case (16 × 64 B ÷ 45.75 ns = 22.4 GB/s), and DDR5 doubled the bank count to 32 to stay at about 86 percent of its own, because the row cycle time did not improve and the data rate did. The CAS latency guide works these timings in full.

Populate every channel first

None of the per-channel arithmetic survives an unbalanced configuration.

EPYC 9004, 12 channels, DDR5-4800

12 modules   12 × 38.4 = 460.8 GB/s      100 percent
 8 modules    8 × 38.4 = 307.2 GB/s       67 percent
 6 modules    6 × 38.4 = 230.4 GB/s       50 percent
 4 modules    4 × 38.4 = 153.6 GB/s       33 percent

Populating eight of twelve channels because eight modules were what the budget allowed costs a third of the platform’s memory bandwidth, and the machine will not complain. It can be worse than the table suggests, because an interleave that does not divide evenly across channels either falls back to a smaller interleave group or splits the address space into a fast region and a slow one. Populate all channels first, then add capacity. Twelve small modules beat six large ones on every memory-bound workload at the same total capacity.

When you measure, a loaded-latency curve, such as Intel’s Memory Latency Checker produces, is the measurement that answers a buying question, because it shows if the machine is short of bandwidth or of latency, and those two shortages are fixed by buying opposite things. STREAM’s Triad figure, by contrast, counts 24 bytes per element where the bus carries 32, a third more, unless the code uses non-temporal stores, because a normal store first fetches the line it writes.

What the speed number is worth on the used market

Speed is the field on a used listing most likely to be paid for and not used. A machine on the Xeon E5-2600 v3 generation is validated at DDR4-2133 with one module per channel and DDR4-1866 with two. Registered DDR4 modules exist in quantity at 2133, 2400, 2666 and 3200, from different fleet generations, priced accordingly.

DDR4-2400 module in an E5-2600 v3 machine   runs at 2133     11 percent of its rating unused
DDR4-2666 module in the same machine        runs at 2133     20 percent unused
DDR4-3200 module in the same machine        runs at 2133     33 percent unused

Every cent of the premium above the 2133 part buys nothing in that machine. The reverse mistake costs more: buying 2133 parts for a machine that would have run 2666 gives up 20 percent of peak bandwidth permanently, for a saving usually smaller than 20 percent, because the cheap used grades are cheap for reasons of supply rather than specification.

So find the speed the machine is validated at, at the module count you intend to install, and buy that grade. Not higher, because it is wasted. Not lower, because it is permanent. This site’s server memory listings carry the speed as a facet, with pages per grade such as DDR4-2133 and DDR4-2666, and the compatibility pages carry the validated figure for each machine.

Two exceptions. A higher grade is worth buying if you expect to move it into a faster machine later, because memory does not age in a drawer. And it is worth buying when the price difference has collapsed, which happens whenever a fleet generation is decommissioned in bulk. Sort the DDR4 listings by price per gigabyte to see whether it has; prices move weekly, and Trends follows each generation’s price per gigabyte over the last month.

What a listing can and cannot tell you about speed

Specifications on this site are read from the words of the eBay listing title by fixed rules, which the methodology page sets out. A blank speed field means the title did not state a speed, not that the module has none; a listing that never says 2666 does not get quietly filed as 2666. A speed in a title is the seller’s claim, not a reading from the module. It is usually copied off the label, but a mistyped part number produces a wrong speed that looks exactly like a right one, so look the part number up on the part pages or the manufacturer’s site and check the speed it decodes to. And a title’s speed says nothing about what your machine will run it at.

What cannot be known before you buy

Whether a particular processor will hold a particular profile is not published: memory controllers vary between chips of the same model, and a kit rated DDR5-8000 is a statement about the modules, not about your processor. A module part number does not pin the DRAM inside it, because vendors requalify parts onto new die revisions and die vendors within one part number. And real bandwidth on your workload is not predictable from any specification: peak is multiplication, refresh and the timings set a ceiling below it, and the rest is scheduling in a controller nobody documents.

A memory speed grade is a statement about one interface in one validated configuration. Four different numbers are all called speed: the array clock, the bus clock, the transfer rate and, on an MRDIMM, the host-side rate that no DRAM on the module is running at. Knowing which one a listing quotes, and which one your machine will train to, is the difference between buying the right module and buying a faster one.