DDR to DDR5: every memory module generation compared

Each generation from DDR to DDR5 moved the module’s notch and changed its supply voltage and signaling, so the notch keeps a module out of any slot but its own generation’s. Most generations changed the pin count or pitch as well; DDR3 kept DDR2’s 240 contacts and DDR5 kept DDR4’s 288. Behind the differences is one idea. The DRAM’s internal column path has run at 100 to 550 MHz since 2000; DDR, DDR2, DDR3 and DDR5 each fetched more bits per access (2, then 4, 8 and 16); DDR4 added bank groups instead; and every generation drove the pins faster, which took a module from 3.2 GB/s at DDR-400 to 70.4 GB/s at DDR5-8800 while the wait for the first word stayed between about 12.5 and 18 ns. Along the way the module stopped being a passive card. A DDR5 server module carries its own power supply, a configuration hub, three thermometers and a clock register besides the DRAM; the DRAM itself comes from three companies, mostly in Korea and Taiwan, and every part is built to standards voted in a JEDEC committee.

This is the site’s reference for the module itself: the standards behind it, the electrical changes, the circuit board, every chip on it, what the motherboard has to supply, who makes it and how it is tested, and how to read its label and part number. Where a figure comes from a standard, a datasheet or a filing, the document is named in the text; where it is worked out here, the arithmetic is shown. Which generation to buy is in DDR4 against DDR5, and whether a module fits a given machine in how to check what RAM fits.

The five generations side by side

The peak figures are the data rate times eight bytes. DDR5-8800 is the fastest device speed JEDEC has announced, in JESD79-5C (April 2024); JEDEC’s DDR5 SPD contents standard has coded modules up to DDR5-9200 since October 2025. The DDR5 densities are the range JEDEC’s November 2025 revision lists; Micron’s DDR5 documents plan dies to 64 Gbit.

Sources: JEDEC, JESD79F DDR SDRAM (DDR-400); JEDEC, JESD208 Specialty DDR2-1066 SDRAM; JEDEC, JESD79-3F DDR3 SDRAM (DDR3-2133); JEDEC, DDR4 publication, 25 Sep 2012 (3.2 GT/s); JEDEC, JESD79-5C update, 17 Apr 2024 (8800). Figures as of October 30, 2026. Peak transfer, never reached in use. A DDR5 module's figure is the sum of its two 32-bit subchannels. Over the same span first-word latency stayed between about 12.5 and 18 ns.

Show the figures

One module's peak bandwidth at each generation's fastest JEDEC grade (GB/s per module: the data rate times 8 bytes)

Period	Peak bandwidth per module
DDR-400	3.2
DDR2-1066	8.5
DDR3-2133	17.1
DDR4-3200	25.6
DDR5-8800	70.4

Telling the generations apart from a listing

Four things in a photograph settle the generation before the title does:

1. The label prefix. PC alone with a four-digit bandwidth is DDR (PC3200); PC2-, PC3-, PC4- and PC5- name the rest, and PC3L and PC3U are 1.35 V and 1.25 V DDR3. DDR to DDR3 labels print bandwidth in MB/s (PC3-12800 is DDR3-1600); DDR4 and DDR5 labels print the data rate (PC4-3200AA). MHz against MT/s has the full ladder.
2. The notch. On a DDR3 module it sits well toward one end, 12 mm off center; on DDR2, DDR4 and DDR5 it sits 4 to 6 mm off the middle, and on DDR about 7.6 mm off it, beside visibly wider contacts.
3. The contact edge. DDR, DDR2 and DDR3 edges are straight. DDR4 and DDR5 edges are stepped, the middle contacts half a millimeter lower than the ends, and read as a gentle curve in a photograph.
4. The small chips. A DDR5 module has a power chip with its inductors and capacitors near the middle of the board, which no earlier generation has. A DDR2 FB-DIMM wears a full metal jacket over its buffer chip.

Each generation has its own listings on this site, ranked by price per gigabyte: DDR, DDR2, DDR3, DDR4 and DDR5. For anything the photograph does not settle, how to read labels and part numbers decodes the rest.

Who writes the rules: JEDEC

Almost every DDR module on sale was built to documents from one body: the JEDEC Solid State Technology Association in Arlington, Virginia. It began in 1958 as the Joint Electron Device Engineering Council, inherited from a 1944 council that standardized vacuum tubes and run jointly by the National Electrical Manufacturers Association and the Electronic Industries Association, and it became an independent association under its present name in 1999. JEDEC describes itself in 2026 as “over 400 member companies” with more than 100 committees and task groups; its public member list named 421 distinct companies on October 30, 2026, among them the DRAM makers Samsung, SK hynix, Micron, CXMT, Nanya and Winbond, and Intel, AMD, Nvidia, Apple, Kingston, Corsair, G.Skill and Rambus.

A standard is written by a committee, voted one company one vote, and then approved by the board. Ballots are cast electronically before the meetings, which rotate around the world about four times a year, and comments from the voters are reported at the meetings and can lead to changes in the proposal. The DDR5 standard of July 2020 credited “more than 150” member companies. The chair of the board in 2026, Mian Quddus of Samsung, already held it in May 2006, and he also chairs the module committee.

The memory committee is JC-42 because of a numbering scheme set between 1968 and 1975 that reserved the forties for integrated circuits. The pieces of a DDR module come from different committees:

The chip standards for each generation, with the first publication and the fastest grade the latest revision defines:

DDR3 and DDR5 outgrew their first ceilings; DDR4 grew into its own. DDR3 was published for 800 to 1,600 MT/s and later gained 1866 and 2133; JEDEC’s own DDR4 announcement noted “DDR3 exceeding its original targeted performance”. DDR5 launched at 4,800 MT/s, which JEDEC called “50% higher than DDR4’s end of life speed of 3.2 Gbps”, and has been raised three times since.

JEDEC says it was the first standards group to publish its standards on the web for anyone to download free, in 1997, which its president recalls some in the standards community calling “heresy”. Since January 2018 non-members pay for a small number: in October 2026 the DDR3, DDR4 and DDR5 chip standards cost $247, $284 and $423, while the DDR and DDR2 standards and most module, SPD and label documents remain free with registration. Behind them sits JESD21-C, the module bible, which JEDEC describes as “some 3000 pages” of configurations collected since September 1989. Its archive keeps fossils: the index still titles the DDR4 outlines MO-309 and MO-310 “284 Pin” and “256 Pin”, the pin counts planned before DDR4 shipped with 288 and 260.

Rambus, and the patent rule that followed

Rambus attended JEDEC as a guest in December 1991, joined in February 1992 and withdrew by a letter of June 17, 1996, while the committee was writing the SDRAM standard and surveying features for DDR, which it adopted in 1998, after Rambus left. From 1999 it told DRAM and chipset makers that it held patents covering them. The US Federal Trade Commission’s complaint of June 2002 called that a failure to disclose; an administrative judge dismissed it in February 2004, the Commission reversed him unanimously in an opinion dated July 31, 2006 and released August 2; it capped Rambus’s royalties in February 2007, and the D.C. Circuit set the order aside on April 22, 2008, holding that the FTC had not shown JEDEC would have chosen differently. The Supreme Court declined the case in February 2009.

The European Commission settled its own case in December 2009 with commitments: no royalty at all on SDR and DDR, the two standards whose work began while Rambus sat on the committee, and at most 1.5% on DDR2 and DDR3, against the 3.5% Rambus had charged on DDR. The private suits ended in licenses: Samsung’s in January 2010 worth about $900 million in cash, quarterly payments and a share purchase, SK hynix’s in June 2013 at $240 million and Micron’s in December 2013 at up to $280 million. JEDEC rewrote its patent policy in June 2010: every participant must disclose patents it knows to be potentially essential and commits to license them on reasonable and non-discriminatory terms, unless it gives notice and leaves the committee. Rambus is a JEDEC member again in 2026, and one of its engineers is vice-chair of JC-40.1, the subcommittee that writes the DDR5 SPD hub and PMIC standards.

What JEDEC does not govern

Overclocking profiles are outside the standard. When Nvidia and Corsair published EPP in 2006, JEDEC issued a position statement that it was “not a JEDEC endorsed specification” and that it reused SPD bytes reserved for the manufacturer. Intel’s XMP (DDR3 in 2007, XMP 3.0 for DDR5 with five profiles, two of them user-writable, and module voltage control) and AMD’s EXPO for Socket AM5 live in the same vendor area. A module first boots at its JEDEC settings, and both Intel and AMD say enabling a profile can void the processor warranty. MHz against MT/s covers what a profile changes.

Qualification lists are a second gate. Intel’s platform memory validation is voluntary for suppliers, is run, as it was before DDR5, by approved outside labs that suppliers pay, Advanced Validation Labs among them, and Intel says it is “not intended to replace the normal product qualification process”. Motherboard makers publish kit-by-board lists that change with each BIOS. HPE’s SmartMemory, from ProLiant Gen8 on, authenticates HPE-qualified modules and reserves some memory features for them, which is why a module that is electrically identical can draw a warning in an HPE server. Before DDR, Intel wrote module rules itself: PC100 began as an Intel specification, PC133 followed it, and both were designs that JEDEC absorbed; JESD21-C still carries a “168 Pin PC133 SDRAM Registered DIMM” design.

The law around a module

• Lead. EU Directive 2002/95/EC, RoHS, barred lead, mercury, cadmium, hexavalent chromium and two flame retardants from new equipment placed on the market from July 1, 2006, with a temporary exemption for server solder. Module assembly moved to lead-free tin-silver-copper solder in the middle of DDR2’s life, and JEDEC wrote the reflow and marking standards for it with IPC.
• Gold and tin. The US SEC’s conflict-minerals rule of August 22, 2012, under Dodd-Frank’s conflict-minerals provision, made listed companies report the origin of tantalum, tin, tungsten and gold. A DIMM’s edge contacts are gold and its solder is tin.
• Price-fixing. The US Justice Department proved a DRAM cartel that ran from April 1999 to June 2002: Infineon paid $160 million, Hynix $185 million, Samsung $300 million, then “the second largest criminal antitrust fine in U.S. history”, and Elpida $84 million: $729 million from the four companies, and more than $730 million with the fines on executives. The European Commission settled with ten producers in May 2010 and fined nine of them €331 million, its first cartel settlement; Micron, which reported the cartel, was immune.
• Export controls. A US rule of October 7, 2022 required licenses to supply Chinese fabs making DRAM at an 18 nm half-pitch or finer. A December 2024 rule replaced the half-pitch test with cell area (below 0.0019 µm²) or bit density (above 0.288 Gbit per mm²) and added HBM, because denser cell layouts and stacking raised density without shrinking the pitch. CXMT builds without EUV for an older reason: the Netherlands has not licensed ASML’s EUV scanners for export to China since 2019.

Inside the chip: how each generation got faster

The memory array barely sped up; the prefetch did the work

A DRAM’s internal column path has run at 100 to 550 megahertz since 2000. What changed is how many bits each access fetches per pin, which lets the pins run faster than the array. The column-cycle rate below is the data rate divided by the prefetch, worked out from each generation’s JEDEC range:

Micron’s DDR5 introduction (May 2019) puts it plainly: the 16n prefetch “enables higher data rates while keeping the internal core clock range similar to DDR4”. The cost is that the time to the first word does not fall:

first-word latency = CL × 2,000 ÷ data rate (ns)

  DDR-400    CL3    3 × 2000 ÷  400   = 15.00 ns
  DDR2-800   CL5    5 × 2000 ÷  800   = 12.50 ns
  DDR3-1600  CL11  11 × 2000 ÷ 1600   = 13.75 ns
  DDR4-3200  CL22  22 × 2000 ÷ 3200   = 13.75 ns
  DDR5-4800  CL40  40 × 2000 ÷ 4800   = 16.67 ns
  DDR5-6400  CL52  52 × 2000 ÷ 6400   = 16.25 ns

Twenty-two times the bandwidth, and roughly the same 12.5 to 18 ns to the first word. CAS latency explained takes the timings apart; the point here is that every generation spent its new transistors on width and parallelism, never on a faster cell.

Banks, bank groups, and two channels on one stick

DDR had four banks, DDR2 four or eight, DDR3 eight. DDR4 hit a wall that bank groups exist to climb: at 3,200 MT/s an eight-transfer burst lasts 2.5 ns, shorter than one group of banks can turn a column command around. DDR4 splits its sixteen banks into four groups (an x16 chip has eight banks in two), and back-to-back reads to different groups need only four clocks (tCCD_S) while reads within one group wait longer (tCCD_L). DDR5 doubled both again, to 32 banks in eight groups on x4 and x8 chips with dies of 16 Gbit and larger, and doubled the burst to sixteen.

That burst length is why a DDR5 module is two memory channels. Sixteen transfers on a 32-bit path deliver 64 bytes, one processor cache line, so each half of the module can serve a request on its own. JEDEC’s DDR5 release described “two 40-bit fully independent sub-channels on the same module”, 32 data bits and 8 check bits each on a server module, and Micron called the result “essentially turning an 8-channel system… into a 16-channel system”. The module still has 64 data bits; they are no longer one bus. Ranks and 3DS covers how ranks sit on those subchannels, and DDR4 against DDR5 what it is worth in a desktop.

Voltage and signaling: from SSTL to pseudo open drain

DDR through DDR3 terminated their lines at a midpoint, using JEDEC’s stub series terminated logic on DDR and DDR2 and a 1.5 V center-terminated push-pull interface, often called SSTL_15, on DDR3: lines terminated to a midpoint at half the I/O voltage, through resistors to a VTT rail or, for data from DDR2 on, through on-die resistors split between the supply and ground, with a reference at the same midpoint that every receiver compared against. DDR4 switched the data bus to pseudo open drain, terminated to VDDQ itself, so a line held high draws no termination current and only a low costs power. Two consequences followed. The eye is no longer centered on half the supply, so a fixed reference stopped working and each DRAM now generates and trains its own VrefDQ. And it became worth inverting a byte that holds more zeros than ones, which is data bus inversion. DDR5 kept pseudo open drain at 1.1 V, moved the command and chip select references inside the chip as well, added equalization to the data receivers, and replaced the module’s discrete termination resistors with termination inside the DRAM.

DDR4’s third supply removed a circuit. The 2.5 V VPP pin feeds the word lines that switch each cell’s transistor, and Micron says it “replaces the internal word-line charge pumps that were present in earlier versions”. DDR3L is a dual-voltage part in most cases: Micron’s DDR3L runs at 1.35 V and is “backward compatible” to 1.5 V, which is why a DDR3L module works in most DDR3 machines and a plain DDR3 module is out of specification, and often fails, in a board that supplies only 1.35 V. JEDEC warns that “not all devices will be interoperable at both voltage ranges”. Samsung’s M393B1K70DH0-YH9 is a DDR3L registered module, sold as PC3L.

What each generation added, and the problem each one solved

On-die ECC is not ECC memory. It corrects single-bit errors inside each chip before data leaves it, signals nothing as it corrects, and reports at most an error count after a full scrub; a module only has ECC if it carries extra chips for check bits. ECC against non-ECC is the home for that difference.

Refresh, the tax that grows with density

A DRAM cell is a capacitor that leaks, so every row is rewritten on a schedule. DDR through DDR4 issue a refresh every 7.8 µs, and DDR2 through DDR4 twice as often above 85 °C; DDR5 refreshes every 3.9 µs, its whole array every 32 ms. While an all-bank refresh runs, the chip answers nothing, and the time it takes grows with the die:

refresh tax = tRFC ÷ tREFI

  DDR    512 Mbit   70 ns ÷ 7,800 ns   = 0.9%
  DDR2   1 Gbit    127.5 ns ÷ 7,800 ns = 1.6%
  DDR3   8 Gbit    350 ns ÷ 7,800 ns   = 4.5%
  DDR4   16 Gbit   550 ns ÷ 7,800 ns   = 7.1%
  DDR5   16 Gbit   295 ns ÷ 3,900 ns   = 7.6%   (all banks)
                                      130 ns, same-bank: 24 of 32 banks keep working

The figures are from Micron’s datasheets, except 16 Gbit DDR4, where 550 ns is JEDEC’s default and makers may specify 450 or 350 ns (Micron’s own 16 Gbit chip is rated 350). DDR5’s same-bank refresh is the answer to that curve: it refreshes one bank in each group while the other banks keep serving requests, and Micron’s November 2019 simulations put the gain at 6% to 9% of throughput. The other answer, written into JESD79-5C in 2024, is security rather than speed: Per-Row Activation Counting lets the DRAM count how often each row is opened and ask the controller for time to protect its neighbors, the rowhammer defense, and the same revision deprecated partial-array self refresh “to address security concerns”.

The module as a physical object

Pins, pitch and the notch

A full-size DIMM has been 133.35 mm long, exactly 5.25 inches, in every generation. The pin count grew inside that length by narrowing the contacts. The notch positions below were worked out from Micron, Samsung and Advantech module drawings, counting contacts and pitch from the pin-1 end, and they reproduce the distances those drawings print:

The notch wanders so that the wrong module cannot be pushed in. DDR’s original JESD21-C pages even used it to encode voltage, with three positions reserved for 2.5 V, 1.8 V and a third left to be decided, which another page of the standard assigns to 3.3 V. DDR2 and DDR3 have the same 240 contacts at the same pitch and keep apart by putting the notch on opposite sides of center; Wikipedia’s DDR3 article, as read on October 30, 2026, adds that DDR2’s side notches are rounded and DDR3’s square. The FB-DIMM has the same 240 contacts at the same pitch as DDR2, with a different pinout, and has its own key, 4 mm along, so it cannot enter an ordinary DDR2 slot. DDR4 unbuffered and registered modules share one notch, so a server module seats in a desktop slot and most desktop boards will not start; DDR5 gave unbuffered and registered modules different notches, which registered against unbuffered explains; the two also take different input voltages, 5 V and 12 V. Forcing the wrong module risks the socket, which is soldered to the board; what RAM fits covers that.

DDR4’s curved edge is a 0.5 mm step. Micron’s DDR4 RDIMM drawing shows the middle contacts half a millimeter lower than the end ones, with 10.2 mm ramps between, so the socket’s springs engage progressively instead of all at once; DDR5 kept it. Heights grew to 31.25 mm on DDR4 and DDR5, and very-low-profile server modules for blades and 1U machines are 18.75 mm.

How many of the contacts are power and ground

Counted from the pin tables of Micron’s and Advantech’s datasheets. A DDR5 server module takes its whole power budget through three contacts, and nearly half of its edge is ground, the return path that lets the signal contacts run at 4,800 MT/s and above. At the 717 mA worst case Micron gives for a 32 GB DDR5 RDIMM, each 12 V contact carries about 0.24 A, against a 0.75 A rating on TE Connectivity’s DDR4 server socket.

Sockets and the gold edge

Every Micron module datasheet lists gold edge contacts. Advantech specifies 30 microinches (about 0.76 µm) of gold on its DDR5 module edge, and TE’s DDR4 socket puts 15 microinches over a nickel underplate on its own contacts. A server DIMM socket is not built for many insertions: TE’s 2015 specification for its DDR4 surface-mount server socket rates it for 25 mating cycles at up to 106.8 N of insertion force, about 24 pounds.

Laptops, and what replaces the SO-DIMM

SO-DIMMs are 30 mm tall and about half a DIMM’s length, and each generation changed the count: 200 contacts on DDR and DDR2, with the notch moved between them, 204 on DDR3, 260 on DDR4 and 262 on DDR5, whose SO-DIMM is 69.6 mm long. DDR4 laptop and DDR5 laptop modules look almost alike and do not interchange. The successor is not an edge connector at all: JEDEC’s CAMM2 standard, JESD318 of December 5, 2023, defines a compression-mounted module for DDR5 and for LPDDR5 on a common connector with different pinouts, mounted differently to “prevent the mounting of a module where it should not go”. The LPDDR version, LPCAMM2, is 78 × 23 mm across its main body, not counting a mounting tab, and 2.6 mm tall. In servers, Micron and Nvidia’s SOCAMM of March 2025 puts 128 GB of LPDDR5X on a 14 × 90 mm board, a third of an RDIMM’s area; JEDEC standardized SOCAMM2 as JESD328 in June 2026.

How a module’s circuit board is built

Raw cards: JEDEC publishes the board itself

A module’s circuit board is usually a JEDEC reference design. The module committee publishes a design annex for each “raw card”, named by a letter, that “defines the electrical and mechanical requirements” of that board, and JEDEC sells the layout files themselves: the PC4-2400 unbuffered DIMM design, raw cards A1 and D1 for one rank of x8 chips, costs non-members $2,000 and includes the board file. The letter is printed on the module label, and it tells you the arrangement of chips:

Taken from Micron’s module datasheets. The letters are not portable: B is a dual-rank x8 desktop board on DDR2 and a dual-rank x4 server board on DDR4.

Routing: from a tree to a chain to two subchannels

Micron’s module datasheets, from DDR to DDR5, say its boards are designed with “carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling”. The datasheets show what that meant in each generation:

• DDR and DDR2: a tree. Command and address lines branch from the edge to every chip, with the termination off the module on the motherboard. Micron’s DDR2 desktop module puts 22-ohm series resistors on every data, strobe and mask line, 7.5-ohm resistors on address and command, a 67-ohm termination across each clock pair, and capacitors that appear to serve as dummy loads: 25 pF on chip select, clock enable and on-die termination lines and 1 pF on one clock pair, so that lightly loaded nets switch at the same speed as heavily loaded ones.
• DDR3 and DDR4: a chain. In Micron’s words, command, address, control and clock are “routed in a fly-by topology, where each… pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector)”. The resistors to VTT now sit on the module at the end of the chain, and write leveling corrects the skew the chain creates. On Micron’s DDR4 registered module the RCD sits in the center and drives a separate copy of every command line to each half of the board, and each DRAM has its own 240-ohm 1% calibration resistor to ground.
• DDR5: two subchannels on one board. The first subchannel’s chips sit on the pin-1 half and the second’s on the other. On Micron’s 32 GB DDR5 RDIMM the RCD is in the front center, the two temperature sensors at the top corners, and the SPD hub and PMIC at the back center; desktop modules put the hub and PMIC at the top center between the two groups of chips. The termination resistors are gone, replaced by termination inside each DRAM, and Micron’s client modules carry “independent power planes for all UDIMM and SODIMM layouts” for VDD, VDDQ and VPP.

Memory makers’ datasheets do not say how many copper layers a module has, though some enthusiast brands advertise it, TeamGroup for one calling its T-Create Expert CKD DDR5 a 10-layer PCB; the stack-up is in JEDEC’s raw-card files. The edge thickness barely changes: Micron’s drawings give 1.27 ± 0.10 mm, 0.050 inch, for DDR through DDR3, 1.3 to 1.5 mm on its DDR4 registered modules, and 1.20 mm on its DDR5 SO-DIMM. The laminate is glass-epoxy; Micron offers its DDR3, DDR4 and DDR5 modules halogen-free, and its DDR2 part numbers carried a separate letter for lead-free.

Assembly and heat

A module is built like any surface-mount board: solder paste, placement, lead-free reflow, inspection, then the SPD programmed with the module’s identity and the module tested. What changed is how much heat the chips make and where. From the worst-case current tables in Micron’s datasheets:

These are ceilings built from component maxima, not typical draw. The FB-DIMM ran hot even at idle: Samsung rates its 2 GB module at 4.15 W idle, about 2.4 W of it in the buffer chip, which was rated to a 110 °C case against the DRAM’s 95 °C, and FB-DIMMs carried a heat spreader over the buffer alone or a full heat spreader up to 8.2 mm thick. DRAM chips from DDR2 on are rated to an 85 °C case, or 95 °C with refresh doubled, and Micron notes that its DDR5 modules use X5R capacitors rated only to 85 °C, so the weak point on a hot DDR5 module may be a capacitor rather than a chip.

The chips on a module besides DRAM

An unbuffered DDR module was a circuit board, DRAM and one small memory chip. Everything else on the board was passive. Each generation since added silicon, until a DDR5 server module became a small system:

SPD: from a 256-byte EEPROM to a hub

The serial presence detect chip tells the firmware what the module is: its type, size, organization, timings, maker and serial number. AMD’s 2006 BIOS guide for the Athlon 64 is blunt about it: “Non-SPD memory sizing is not supported.” On DDR and DDR2 it was a 2-Kbit (256-byte) I2C EEPROM, about half of it defined by JEDEC, with the maker’s JEP106 code at bytes 64 to 71, the part number at 73 to 90 and a year and week at 93 and 94. Microchip launched its 34AA02 family for “newer DDR2 and future DDR3 modules” in March 2008. DDR3 kept 256 bytes, defined 176 of them, with a CRC over the first 117 or 126; XMP lives in the remaining 80. DDR4 doubled it to 512 bytes and could not address them, so the EE1004 EEPROM presents two 256-byte pages that the host switches with dedicated page commands, which kept older SPD readers working on the first page. DDR5 replaced the plain EEPROM with an EEPROM that is also a hub, the SPD5118 (JESD300-5, 2020): 1,024 bytes in sixteen write-protectable blocks, I2C or the faster I3C-based sideband bus at up to 12.5 MHz, a 1.8 V supply and a built-in temperature sensor. It is a hub because it isolates a local bus on the module from the host’s bus. It records the maker and revision of every other chip on the module: up to three PMICs and the sensors in a common area, and the RCD or clock driver, or on an MRDIMM the MRCD and MDBs, in the bytes for that module type.

Temperature sensors

FB-DIMM put the sensor inside its buffer chip, reading 0 to 127 °C in half-degree steps and able to shut the DRAM interface down above a limit. DDR3 and DDR4 server modules usually carry a JEDEC TSE2002av or TSE2004av, a thermometer and the SPD EEPROM in one 2 × 3 mm package; the DDR4 part from Renesas is accurate to ±0.5 °C typical between 75 and 95 °C and has an open-drain EVENT pin the chipset uses to throttle memory. A DDR5 RDIMM has three thermometers: the one in the hub and two TS5111-class sensors, which Rambus says give “three points of thermal telemetry”. Renesas’s TS5111 of May 2020 is a six-ball chip 0.8 by 1.3 mm.

Registers, PLLs and clock drivers

A register re-drives the command and address bus so the controller sees one load per module instead of every chip. Registered against unbuffered explains why that matters; this is how the hardware changed:

• DDR: Texas Instruments’ January 2003 note on JEDEC Raw Card B describes 18 DRAMs, two SSTV16857 14-bit registers, a CDCV857 PLL clock driver and an SPD EEPROM. The registers were rated 2.3 to 2.7 V, 2.5 to 2.7 V at PC3200.
• DDR2: the SSTU32864 runs as one 25-bit register driving nine DRAM loads or as a 14-bit 1:2 register, two per module driving eighteen, with a separate CU877 PLL.
• DDR3: register and PLL merged into one JEDEC SSTE32882 chip, with command and address parity and a mirror mode for chips on the back.
• DDR4: the registering clock driver, RCD, from IDT, Inphi, Montage and Rambus. IDT announced the first complete DDR4 load-reduced chipset on January 28, 2013.
• DDR5: the RCD drives the two subchannels separately. Rambus lists six generations at 4,800, 5,600, 6,400, 7,200, 8,000 and 9,600 MT/s, and a module’s RCD generation caps its speed.
• DDR5 clocked unbuffered (CUDIMM): a clock driver on a desktop module for the first time. Renesas announced the first one, the RG5C172, in June 2023, and JEDEC’s October 2024 release said the CKD “regenerat[es] the clock signal locally” to raise unbuffered modules from 6,400 to 7,200 MT/s, with 9,200 in later versions. Intel’s Core Ultra 200S is the first desktop platform to support them, rated 6,400 MT/s with CUDIMMs against 5,600 with ordinary UDIMMs.

Buffers: FB-DIMM, load-reduced and multiplexed modules

FB-DIMM was the most ambitious module JEDEC ever standardized, and the hottest of its day. Its Advanced Memory Buffer turned the parallel memory bus into a serial point-to-point link, ten lanes out and up to fourteen back, repeated from module to module, so a channel could chain eight modules and 288 DRAM chips. Intel’s own 6400/6402 AMB datasheet of October 2006 puts the buffer alone at 3.5 to 7.6 W depending on speed, position and whether the module uses x4 or x8 chips, before any DRAM, and it needed its own 1.5 V rail. HP put it at almost 5 W more than a registered DDR2 module, or as much as 80 W for a sixteen-module server. Dell’s PowerEdge 2950 and HPE’s ProLiant DL380 G5 take them, and modules like Samsung’s M395T5750EZ4-CE66 still sell from those machines. Intel’s next large-server design kept a serial link and moved the buffer off the module onto the board: the 7500 Scalable Memory Buffer behind the Xeon 7500, then the 9 W C102 and C104 buffers behind the Xeon E7 v2.

The load-reduced module buffers the data lines as well as the commands. Inphi sampled the first DDR3 isolation memory buffer in January 2010, and DDR3 load-reduced modules carry one central iMB. On DDR4 load-reduced modules the design is distributed: one RCD and nine data buffers, each serving the two x4 chips per rank beside it, which IDT said could reduce up to sixteen ranks to a single electrical load. Samsung’s M386A8K40BM2 is one. DDR5 defined data buffers too, but the load-reduced module barely reached the market.

The MRDIMM is DDR5’s answer instead: one multiplexed RCD and ten multiplexed data buffers (a “1+10” chipset, in Montage’s words of January 24, 2025) that read two ranks at once and send them down the bus at twice the DRAM’s own rate. Montage’s first generation runs 8,800 MT/s and its second 12,800 MT/s. Intel’s Xeon 6900P was the first platform, at up to 8,800 MT/s, with the Xeon 6500P and 6700P at 8,000, and AMD’s EPYC 9006 followed in 2026 at up to 12,800 MT/s. DDR5 MRDIMMs are still rare second hand.

DDR5 put the power supply on the module

Every generation before DDR5 took its working voltages from the motherboard. A DDR5 module takes bulk power and makes its own with a power management IC:

A server PMIC takes 4.25 to 15 V. Texas Instruments’ TPS53830A makes 1.1 V VDD at up to 12 A from two phases, 1.1 V VDDQ at 6 A and 1.8 V VPP at 5 A, and reports voltage, current and temperature over the sideband bus; Renesas rates its P8900 at “up to 15 Watts”. IDT’s December 2019 announcement gave the reason: distributing power management “across each memory module” instead of “centralizing them on the motherboard” helps thermals, reliability and scaling. It also freed the edge connector. Micron’s client module paper counts 26 VDD pins on a DDR4 UDIMM and three 5 V bulk-power pins on a DDR5 one, and 94 ground pins against 122. The cost falls on the second-hand buyer: a DDR5 module has a switching regulator that can fail, which DDR4 against DDR5 weighs.

What the motherboard and processor must supply

The VTT rail needs a regulator that can sink current as well as source it, because a terminated line pulls it either way. Texas Instruments’ LP2995 did it for SSTL-2, its TPS51200 and TPS51206 for DDR3 and DDR4; the TPS51916 combines the VDDQ converter, a 2 A termination regulator and the buffered reference in one chip, and switches termination off in sleep while keeping the DRAM powered. On a DDR5 board none of that exists.

The memory controller moved into the processor

AMD moved it before Intel did. The Opteron launched on April 22, 2003 with the DRAM controller inside the processor, and the Athlon 64 followed in September; AMD’s BIOS guide addresses it as a function of the processor itself. Intel kept the controller in the chipset’s memory controller hub through the Core 2 era, which is why a Core 2 Duo E7000 machine takes DDR2 or DDR3 depending on its board rather than its processor, and why boards built on the same chipset were sold in DDR2 and DDR3 versions. The Core i7-900 moved a three-channel DDR3 controller onto the processor in November 2008, and the Xeon 5500 brought it to servers the following year, behind machines such as the ProLiant DL380 G6 and PowerEdge R710. Once the controller is in the processor, the processor decides the generation; the one modern exception is a controller that speaks two, as on the 12th-generation Core, where the board picks one for good.

Training, and why a new DDR5 machine is slow to start

The firmware reads every module’s SPD over SMBus, picks the fastest settings the slowest module allows, and then trains: it sweeps delays and reference voltages on each line until it finds the middle of the data eye. Each generation added training steps: write and read leveling with DDR3, the internal reference with DDR4, and on DDR5 command, chip-select and equalization training as well. Intel’s reference code runs full training when it has no valid saved results, and restores the saved results on later boots; firmware stores them in flash because memory cannot be used until it is configured. On AMD processors since Family 17h, coreboot’s documentation of that family says, the platform security processor trains DRAM before “the x86 core fetches and executes” its first instruction. A first boot after a memory change is therefore the slow one on any DDR5 machine, and an apparent hang of a minute or more after installing new modules is usually training rather than failure, so give it a few minutes before pulling the modules.

How to read labels and part numbers

A module carries four identities, written by different people at different times: the JEDEC line on its label, the module maker’s part number, the markings lasered onto each DRAM chip, and the bytes in its SPD chip. A genuine module agrees with itself across all four, so reading them against each other is the quickest check on a used one, and most of the codes are more informative than they look. Buying used RAM on eBay covers what to do when they disagree; this is the key to reading them.

The JEDEC line, generation by generation

JESD21-C’s labeling sections, and for DDR5 JESD401-5, define a line that every standard module carries. Its grammar changed with every generation:

Three habits of the grammar trip people:

• The number after PC changed meaning at DDR4. DDR to DDR3 print module bandwidth in MB/s, eight times the data rate (PC3-12800 is DDR3-1600). DDR4 and DDR5 print the data rate itself (PC4-3200, PC5-4800), so “3200” names three different modules: PC3200 is DDR-400, PC2-3200 is DDR2-400, and PC4-3200 is DDR4-3200. Retailers still convert DDR4 back into bandwidth, which is why the same module is sold as PC4-25600.
• The timing field changed form. DDR prints CL, tRCD and tRP with the decimal point removed (25330 is CL 2.5, then 3, 3, then the SPD digit); DDR2 prints all three (555); DDR3 prints CAS latency alone (11); DDR4 and DDR5 print a speed-bin letter instead, decoded in the DDR4 bins and the DDR5 bins.
• The module type is one letter after the speed: U unbuffered, E unbuffered with ECC, R registered, L load-reduced, S SO-DIMM. DDR2 added F for FB-DIMM and P for a registered module with address parity; DDR4 added T for an ECC SO-DIMM. A DDR4 label carries a voltage position after PC4 too, left blank because a blank means 1.2 V operable, the only value the key lists, which is why Samsung’s own example prints PC4 -2400T with a space.

Micron’s DDR5 key names the remaining fields: the four digits are the “JEDEC SPD revision” and the last two letters the “temperature grade”. Stacked DDR5 parts add a letter to the rank field, S for 3DS stacks, as in 2S2Rx4, two package ranks of two-die stacks, which ranks and 3DS decodes.

Samsung

Samsung’s numbers have the same skeleton in every generation: M for a module (K4 for a chip), a digit for the form factor (3 a DIMM, 4 an SO-DIMM), two digits for the module type, one letter for the generation, then depth, a bank and interface digit, organization, die revision, package and PCB revision, a dash, and a temperature letter with a two-character speed code. The generation letter is the fastest check: L is DDR (H on a DDR chip, K4H), T DDR2, B DDR3, A DDR4 and R DDR5.

M393A2K43CB2-CTD     16 GB DDR4 RDIMM (Samsung DDR4 product guide, May 2018)
M 3 93   module, DIMM, x72 288-pin registered
A        DDR4, 1.2 V
2K       depth 2G built from 8 Gbit chips: 2G x 8 bytes = 16 GB
4 3      16 banks, x8 chips
C        component revision C, the fourth: the "C-die"
B 2      flip-chip FBGA package, PCB revision 2
- C TD   commercial temperature; TD = DDR4-2666 at 19-19-19

Samsung’s DDR4 speed codes are two letters, the first a CAS latency on Samsung’s own scale (P 15, R 17, T 19, V 21, W 22, Y 24, A 26, not the JEDEC bin letters) and the second the data rate: PB and RB are 2133, RC and TC 2400, TD and WD 2666, VF and YF 2933, WE and AE 3200 (the second of each pair is the slower, higher-latency grade, such as AE at 26-22-22). On DDR5 its pages show QK and WK for 4800, WM for 5600 and CP and LP for 6400. On a chip number the letter just before the dash is the die revision, and that is literally where “B-die” comes from: Samsung’s datasheet for K4A8G085WB is titled “8Gb B-die DDR4 SDRAM”. On a module number the die letter comes before the package letter and the PCB digit, so the B in M393A2K43CB2 is the package and the module is C-die. Samsung’s DDR5 pages list 128 GB and 256 GB modules built from 3DS stacks (M321RBGA0B40-CWK is 256 GB of 4-high stacks, 40 packages), and a 96 GB module, M321RYGA0PB0-CWM, built from 24 Gbit chips.

SK hynix

SK hynix modules start HM and the next letter is the generation: HMT is DDR3, HMA DDR4 and HMC DDR5; its chips are H5TQ or H5TC (DDR3), H5AN (DDR4) and H5CG (DDR5).

HMA81GU6AFR8N-UH     8 GB DDR4 desktop module (SK hynix DDR4 module decoder, June 2017)
HM A     SK hynix module, DDR4
8        8 Gbit chips
1G       depth 1G: 8 GB
U 6      288-pin unbuffered, x64 standard height
A        die generation A, the second
F R      FBGA single-die package, lead- and halogen-free
8        x8 chips
N        commercial temperature, 1.2 V
-UH      DDR4-2400 at 17-17-17

Its DDR4 speed codes: TF 2133, UH 2400, VK 2666, WM 2933 and XN 3200, the JEDEC timings, with UL (20-18-18) and VN (22-19-19) as slower grades whose timings match stacked (3DS) parts. The DDR5 numbers go further and name the chips on the module:

HMCG88AEBRA + 3 digits + N    32 GB DDR5 RDIMM (SK hynix DDR5 decoder, October 2020)
HM C     SK hynix module, DDR5
G8       32 GB (G7 16 GB, G9 64 GB, T0 128 GB, T1 256 GB)
8        x8 chips
A        die generation A, the second
EB       DDR5-4800, 40-40-40 in the 2020 decoder (40-39-39 from 2021)
R        RDIMM
A        16 Gbit chips, standard height, 0 to 95 °C
3 digits the register and PMIC makers: 102 Renesas and Renesas,
         105 Montage and Montage, 108 Rambus and a Texas Instruments PMIC
N        normal sale

On a desktop module, which has no register, the same three digits name the PMIC alone: SK hynix’s March 2021 DDR5 UDIMM datasheet gives 081 and 092 for a Renesas PMIC5100 and 084 and 095 for one from MPS. Its DDR4 labels print a separate option code after the part number that names the register and buffer maker (Montage, TI, IDT or Inphi), and the same two letters mean different makers on a DDR3 label, so read the code against the generation.

Micron

Micron’s module numbers lead with the DRAM die count, which is the most useful thing on any label: MT36… has 36 DRAM dies, MT18… 18. DDR4 inserts A after MT and DDR5 inserts C. On DDR to DDR4 a voltage letter follows the count (V 2.5 V DDR, H 1.8 V DDR2, J 1.5 V and K 1.35 V DDR3, A 1.2 V DDR4); on DDR5 that letter is the module supply, F for 12 V or C for 5 V.

MTA36ASF8G72PZ-3G2   64 GB DDR4 RDIMM (Micron module numbering guide)
MT A     Micron, DDR4
36       36 dies
A SF     1.2 V; FBGA chips with a temperature sensor
8G 72    8 Gig words x 72 bits: 8G x 8 bytes = 64 GB, plus ECC
P Z      288-pin RDIMM; commercial temperature, halogen-free
-3G2     DDR4-3200, 22-22-22
36 x4 chips on a 72-bit bus = two ranks of 16 Gbit x4 chips (2Rx4)

MTC40F2046S1RC56BG1  64 GB DDR5 RDIMM
MT C     Micron, DDR5
40       40 dies
F        12 V module supply (C would be 5 V, a client module)
2 0 4    2 package ranks, no stacking, x4 chips
6        64 GB
S 1      standard height, single-die packages
R C      288-pin RDIMM, 80 bits wide; commercial temperature
56B      DDR5-5600 bin B, 46-45-45
G 1      die revision G, PCB revision 1

Three Micron details are worth knowing. The same suffix means different speeds in different generations: -2G3 is DDR3-2133 on a DDR3 module and DDR4-2400 on a DDR4 one. Micron prints a process code after the part number on its labels that names the support chips: on a DDR4 registered module the first letter is the register’s maker and the second the temperature sensor’s (QG is a Montage register and an IDT sensor), and on a DDR5 RDIMM the letters name the PMIC, the register, the SPD hub and the sensor in turn. And Micron does not print its full part number on an FBGA chip: the package carries a five-character code such as D9WFJ, which Micron’s online decoder turns into MT40A512M16LY-062E:E, an 8 Gbit DDR4 chip, die revision E.

Kingston, Crucial, Corsair and G.Skill

Kingston publishes a full decoder, and its DDR5 server modules name every chip supplier in the part number. A ValueRAM number reads speed, type, CAS latency, ranks, width and capacity: KVR32S22S8/16 is a DDR4-3200 SO-DIMM, CL 22, single rank of x8 chips, 16 GB. A Server Premier DDR5 number goes much further:

KSM56R46BD4PMI-64HAI    Kingston Server Premier DDR5 (Kingston's part-number decoder)
KSM 56   Server Premier, DDR5-5600
R        registered, EC8 (80-bit); P would be EC4, 72-bit
46B      CL 46-45-45
D 4      dual rank, x4 chips
P        PMIC by MPS
M        SPD hub by Montage
I        temperature sensor by Renesas
-64      64 GB
H A      SK hynix DRAM, A-die
I        register by Renesas

Kingston’s FURY numbers decode the same way (KF556C36BBEAK2-32 is a DDR5-5600 CL 36 desktop kit, Beast, black, EXPO and XMP, RGB, two modules, 32 GB in all), but name no DRAM maker. Corsair puts the generation in the middle: CMK32GX4M2E3200C16 is Vengeance LPX (K), 32 GB in all, DDR4 (X4), two modules (M2), version E, 3,200 MT/s with XMP on, CL 16; on DDR5 a C before the latency means an XMP kit and a Z an EXPO one, and Corsair identifies the DRAM maker on the label’s version number instead (V3 Micron, V4 Samsung, V5 SK hynix). G.Skill prints capacity per module on DDR5 but per kit on DDR4: F5-6000J3038F16GX2-TZ5NR is DDR5-6000, CL 30-38-38, 1.35 V (the F; A is 1.10 V and each letter adds 0.05 V), two 16 GB modules, Trident Z5 Neo RGB. Crucial publishes no decoder; its DDR5 numbers read as capacity, data rate, CAS latency, type and generation (CT32G48C40U5 is 32 GB DDR5-4800 CL 40 unbuffered, from Crucial’s listing).

A gaming kit’s headline speed is a profile, not what it boots at. Every one of these kits starts at the JEDEC speed in its SPD, usually DDR5-4800 or DDR4-2133 or 2400, until XMP or EXPO is switched on; ValueRAM and Server Premier print the JEDEC speed itself. MHz against MT/s covers the profiles.

Server makers’ numbers

HP, Dell and Lenovo sell memory under their own numbers, and one OEM number covers modules from several DRAM makers: it specifies capacity, ranks, speed and timing, not a supplier. Resellers pair HPE’s assembly number 840756-091 with a Samsung module and its spare 868842-001 with an SK hynix one. In HPE Community threads, -B21 is the orderable option number (one member calls it the North American one) and -001 the spare part; resellers call the -091 number printed on the module’s label the assembly number, and listings use any of the three for the same stick. Lenovo goes further in its own guidance: a part labeled 4800 MT/s may be a 5600 MT/s module, and the server’s UEFI firmware may need an update to support it. To learn what an OEM module actually is, read the DRAM maker’s own number on the label or the SPD’s “DRAM manufacturer” field; this site’s part pages list modules under both kinds of number.

The chips themselves

Every DRAM package carries its maker’s mark, and the maker’s component number decodes the die: Samsung’s K4A8G085WC-BCTD is an 8 Gbit DDR4 x8 chip, C-die, DDR4-2666; SK hynix’s H5AN8G8NAFR-UHC an 8 Gbit DDR4 x8, A-die, DDR4-2400. Micron’s FBGA code needs its decoder, but the top row of a Micron chip decodes by hand: a digit for the year, a letter for the even-numbered work week (A is week 2, Z week 52), the die revision, and two country codes, the first where the wafer was made and the second where the chip was packaged (1 USA, 2 Singapore, 4 Japan, 5 China, 7 Taiwan, 8 Korea, D Malaysia). The year is a single digit, so a 2 is 2012 or 2022.

Micron’s SpecTek division sells graded components under their own marks, and the grade says how they were tested. Its October 2026 buyer’s guide lists PRN and PRM parts as “fully tested & speed graded” at about 99% yield with a 90-day warranty, TP parts at about 90%, and PG, “partially good” components, at about 50% with the note “customer must test”. A module built from TP or PG chips can work perfectly, and has been tested only as well as its assembler tested it, which is the honest summary of every gray-market module: the chips’ grade sets the floor, the module maker’s test decides the rest.

The SPD: the identity inside

The SPD records who built the module and, from DDR3 on, who made its DRAM, as JEDEC JEP106 codes: in DDR3, DDR4 and DDR5 SPDs Samsung reads 80 CE, Micron 80 2C, SK hynix 80 AD, Kingston 01 98, Corsair 02 9E, G.Skill 04 CD and Crucial 85 9B. decode-dimms on Linux (DDR4 and older; it has no DDR5 decoder) and CPU-Z on Windows print both as module and DRAM manufacturer, beside the SPD’s part number and a manufacturing year and week. The SPD part number is free text of 18 to 30 characters and need not match the sticker; Kingston’s labels also carry an internal bill-of-materials number (such as 9965757-004.A00G), which Kingston also uses in its change notices and which is often what the SPD’s part-number field holds in place of the sticker’s ValueRAM number. When the label, the SPD and the chips agree, the module is what it says. When they do not, none of the three settles it alone, though they are not equally easy to fake: a label takes a printer, an SPD an I2C write, and the chips a remarking or a new set of packages.

DDR4 modules in depth

DDR4 shipped in servers and high-end desktops in 2014 and on mainstream desktops from 2015, ran at 1,600 to 3,200 MT/s on 1.2 V, and is still the largest pool of used memory on this site: retired servers supply registered DDR4 in bulk, and every Intel desktop processor from the 6th generation to the 14th on a DDR4 board, and every AM4 Ryzen, takes unbuffered DDR4. This is the reference for the modules themselves; whether to buy DDR4 at all is in is DDR4 still worth buying.

DDR4 speeds and timings: every JEDEC bin

JESD79-4C defines seven data rates and 24 bins. A DDR4 bin letter stands for the same CAS latency at every data rate, which makes the label easy to read once the alphabet is known: J is CL 10, K 11, L 12, M 13, N 14, P 15, R 16, T 17, U 18, V 19, W 20, Y 21, AA 22 and AC 24, and the letters O, Q, S, X, Z and AB are never used. Each bin is CL, tRCD and tRP all equal:

Every maker’s mainstream module sits on the middle bin: Samsung’s and SK hynix’s module tables list 2133P, 2400T, 2666V, 2933Y and 3200AA and none of the faster optional bins, and Micron’s adds only 2400R and 2666U, which is why a server label reads PC4-2933Y or PC4-3200AA and why first-word latency stays near 14 ns from DDR4-2133 to DDR4-3200. The first edition of 2012 defined only 1,600 to 2,400 MT/s, with 2666 and 3200 marked “Reserved”; JEDEC’s announcement called 3.2 GT/s its “initial maximum objective”, and it stayed the ceiling. Two refinements:

• Stacked 3DS modules carry a slower CL under the same rate. Micron’s 3DS grades run 2400 at 20-18-18, 2666 at 22-19-19, 2933 at 24-21-21 and 3200 at 26-22-22, and HPE sells a 128 GB octal-rank load-reduced module at “DDR4-2400 CAS-20-18-18”. Samsung’s second set of DDR4 codes (TC, WD, YF, AE) follows the same pattern, a higher CL over the standard tRCD and tRP.
• A gaming kit’s SPD defaults to a JEDEC bin; its box speed is an XMP profile stored beside it. Kingston’s FURY KF432C16BB1/16 is sold as DDR4-3200 CL16, and its datasheet says the SPD is “programmed to JEDEC standard latency DDR4-2400 timing of 17-17-17 at 1.2V”; its first XMP profile is 3200 at 16-18-18 and 1.35 V (the second is 3000 at 15-17-17). Until XMP is switched on, the kit is DDR4-2400T. DDR4-3200, DDR4-2666 and DDR4-2400 list the JEDEC grades this site ranks.

How big a DDR4 module can be

Capacity is chip density times the number of data chips, and DDR4’s chips run from 4 to 16 Gbit in practice (the standard also defines 2 Gbit):

There is no 64 GB DDR4 desktop module. The densest DDR4 die in the standard is 16 Gbit, a client controller addresses two ranks per channel at one module per channel, and two ranks of eight 16 Gbit chips make 32 GB; that is why Intel’s mainstream two-channel DDR4 desktops from the 8th to the 14th generation top out at 128 GB in four slots (the eight-slot Core X-series i9-10980XE takes 256 GB). The largest DDR4 module of any kind is the 256 GB 3DS RDIMM, which machines such as Lenovo’s ThinkSystem SR650 V2 take 32 at a time for 8 TB; the 512 GB “DIMMs” in the same server guides are Intel Optane persistent memory, not DRAM. The site ranks every size from 16 GB through 32 GB, 64 GB and 128 GB to 256 GB.

DDR4 module types

• UDIMM (288 pins) and SO-DIMM (260 pins, 30 mm tall): desktops and laptops, 2 to 32 GB, never x4 chips. DDR4 laptop.
• ECC UDIMM and ECC SO-DIMM: the same with a ninth chip per rank, for workstations and small servers such as the Xeon E3 and E-2100 lines. DDR4 ECC.
• RDIMM: a registering clock driver in the middle, 8 to 64 GB planar, the bulk of the used market; also in an 18.75 mm very-low-profile version for blades. DDR4 registered.
• LRDIMM: an RCD plus nine data buffers, 32 to 128 GB. DDR4 load-reduced.
• 3DS RDIMM and LRDIMM: through-silicon-via stacks of two, four or eight dies per package, 64 to 256 GB. Samsung announced on August 27, 2014 that it had begun mass-producing the first, a 64 GB module of 36 four-die packages.

Server makers forbid mixing them. Lenovo’s guides say “Mixing different types of memory (RDIMMs, LRDIMMs, 3DS RDIMMs) is not supported”, and a DDR4 unbuffered module in a registered system, or the reverse, fails to train rather than running slowly; registered against unbuffered explains why the two share a notch on DDR4 and do not on DDR5.

DDR4 dies: B-die and the rest

“B-die” is a revision letter, not a grade. Samsung’s DDR4 ordering legend counts die revisions “M: 1st Gen., A: 2nd Gen., B: 3rd Gen., C: 4th Gen., D: 5th Gen.”, so its 8 Gbit B-die is simply the third version of that chip, and the letter sits in both the chip number (K4A8G085WB) and the module number (the letter after “43” in M378A1K43BB2). Its enthusiast reputation, tight timings at high speed and scaling with voltage, is owners’ testing, not Samsung’s claim: Samsung itself rated the 8 Gbit B-die chip no faster than DDR4-3200 CL 22, sold its own B-die modules only up to DDR4-2666 CL 19, and listed those modules and its PC and server B-die chips end of life in the first half of 2019. Every DDR4-3600 and 4000 kit built on it was a module maker’s binning plus an XMP overvolt.

Micron puts the die revision after a colon in the chip number (MT40A1G8SA-062E:E is its 8 Gbit “Rev. E”, the other die enthusiasts sought), and its 8 Gbit chip came in revisions A, B, D, E, G, H, J and later R, its 16 Gbit in B, E and F. SK hynix puts it after the N (H5AN8G8NCJR is an 8 Gbit C-die, and its RDIMM HMA82GR7CJR8N is “based on 8Gb C-die”). On a module, the chips’ own markings or an SPD reader name the die; how to read part numbers has the codes.

Which processors take which DDR4

The official speed is the processor maker’s; on many platforms it falls when a channel holds two modules, and further when those are dual-rank:

Eight channels of DDR4-3200 is 204.8 GB/s per socket, the figure AMD prints for EPYC 7002 and 7003. Machines like the PowerEdge R740 and ProLiant DL380 Gen10 are where most used DDR4 RDIMMs come from.

Is DDR4 being discontinued?

DDR4 is still made in late 2026, by fewer makers and in short supply. Micron had sent end-of-life notices for DDR4 to its high-volume customers by mid-2025, and its June 2026 earnings presentation says the DDR4 it still makes at its Manassas, Virginia fab is for “the legacy product needs of our customers in auto, industrial, medical, aerospace and defense markets”; Samsung and SK hynix were reported in 2025 to be ending DDR4 and then to be extending it into 2026, but by January 2026 TrendForce said Samsung was keeping to its end-of-life plan and SK hynix had moved its Wuxi fab to a newer node as it moved away from DDR4. TrendForce tied Nanya’s and Winbond’s growth at the end of 2025 to DDR4 and DDR3. The supply cut inverted the usual price order. TrendForce reported in August 2025 that in July, 8 GB DDR4 PC modules had become dearer than 8 GB DDR5 ones, and its spot quotes of October 30, 2026 put a 16 Gbit DDR4 chip at $82.80 against $61.50 for a 16 Gbit DDR5 chip, though a whole 16 GB DDR4 desktop module, which holds eight such chips but is built from stock bought months earlier on a thin spot market, traded below a DDR5 one again ($165.60 against $240 on module spot, October 19). Both platforms that use DDR4 were kept alive for it: TrendForce reported in June 2026 that AMD had brought the AM4 Ryzen 7 5800X3D back at Computex and that Intel would keep supplying DDR4-capable Raptor Lake processors. The 2026 DRAM shortage explains the market, and Trends follows used DDR4 prices day by day.

DDR5 modules in depth

DDR5 reached desktops with Intel’s 12th generation in November 2021 and AMD’s AM5 in September 2022, and servers with the 4th-generation Xeon Scalable and EPYC 9004. It is the current generation and the one still changing: its JEDEC ceiling went from 4,800 to 8,800 MT/s, it added clocked, multiplexed and half-width modules, and its dies went from 16 to 32 Gbit in four years.

DDR5 speeds and timings: every JEDEC bin

DDR5 bins work differently from DDR4’s. A DDR5 letter is a rank within one data rate, not a CAS latency: Micron’s DDR5 datasheet defines four bins at every rate, AN fastest, then B, BN and C, and B is the one modules ship at, with a minimum first-word latency (tAA) of 16.000 ns from DDR5-4000 up and 16.250 ns at 3200 and 3600; rounded up to an even CL, that comes to 16.0 to 16.7 ns:

From Micron’s DDR5 core datasheet; JEDEC’s own 2020 tables name the same rates A, B and C. DDR5 allows only even CAS latencies, so a timing that works out to 39 clocks is rounded to 40 for CL while tRCD and tRP keep 39: hence 40-39-39. The labels that matter are PC5-4800B, PC5-5600B and PC5-6400B, and a module label usually carries B, though Micron’s label guide shows a 256 GB stacked RDIMM at 5200C. 3DS stacks run a higher CL at the same letter (4800B is 46-39-39 stacked). Anything faster than the table, or tighter than the AN column, is an XMP or EXPO profile. CAS latency covers why the bins land on 16 ns, and the site ranks DDR5-4800, DDR5-5600, DDR5-6400 and the faster DDR5-7200 and DDR5-8000 separately.

DDR5 module types: UDIMM, CUDIMM, RDIMM, MRDIMM and the rest

A few of these deserve a sentence each:

• The 287-pin module. Micron’s DDR5 UDIMM datasheet marks contact 220 “no pin present” on modules rated 6,400 MT/s and above, and its numbering guide lists its clocked UDIMMs as 287-pin and its RDIMMs as 288 or 287-pin. Micron gives no reason, and the module still fits the same socket.
• CUDIMM. Kingston’s explanation is the plain one: “Beginning with the introduction of 6400MT/s DDR5, a Client Clock Driver (CKD) component must be added”. Intel’s Core Ultra 200S runs CUDIMMs at 6,400 MT/s against 5,600 for ordinary UDIMMs, and its 2026 “S Plus” parts at 7,200; AMD’s AM5 boards accept CUDIMMs with the clock driver in bypass, at the board’s usual speed, though MSI says support varies by processor series and that some processors may fail to boot.
• HUDIMM. On April 17, 2026 ASRock announced support on its Intel 600, 700 and 800-series boards for a DDR5 module with “One sub-channel (1*32-bit)”, co-developed with TeamGroup, whose general manager said it “can half the chip quantity on RAM stick”. It is ASRock’s and TeamGroup’s design, “patent pending”, not a JEDEC standard, and half the width means half the bandwidth.
• EC4 and EC8. A DDR5 RDIMM is usually 80 bits wide, eight check bits per subchannel, so a rank of x4 chips is 20 chips and of x8 chips 10. Some are 72 bits wide, four check bits per subchannel: Samsung’s M329R and Micron’s “P” types, Lenovo’s “9x4” RDIMMs, and every DDR5 ECC UDIMM, though an ECC UDIMM built from x8 chips still carries ten per rank (Micron’s 16 GB one, MTC10C1084S1EC48BA1, has ten dies), so a chip count alone does not tell 72 bits from 80. A desktop ECC module is never 80 bits.
• MRDIMM. JEDEC’s July 2024 plan is “up to twice the peak bandwidth of native DRAM” on the RDIMM form factor and pinout. Intel’s Xeon 6900P runs MRDIMMs at up to 8,800 MT/s against 6,400 for RDIMMs, and the Xeon 6500P and 6700P at 8,000; AMD announced its EPYC 9006 in July 2026 with MRDIMM support up to 12,800 MT/s. DDR5 MRDIMM listings are still few.

Why DDR5 comes in 24, 48 and 96 GB

DDR5 introduced a die that is not a power of two. SK hynix shipped the first 24 Gbit DDR5 samples on December 15, 2021, built on its 1a node with EUV, and said the “initial offerings on this product are set to be 48 Gigabyte (GB) and 96GB modules”. A 24 Gbit chip holds 3 GB, so the same layouts that give 16 and 32 GB from 16 Gbit chips give 24 and 48 GB:

Platforms had to learn the new sizes: Intel’s 13th and 14th-generation datasheet lists 24 Gbit support as added after launch, and the Core Ultra 200S lists 16, 24 and 32 Gbit. The largest ordinary desktop UDIMM in 2026 is 64 GB, two ranks of 32 Gbit chips, which is why Intel’s Core Ultra 9 285K and AMD’s Ryzen 9 9950X both list 256 GB in four slots. On servers, 128 GB no longer needs stacking: Samsung’s 32 Gbit DDR5 of September 1, 2023 was announced as enabling “128GB DRAM module production without the TSV process”. At the top, SK hynix announced on December 17, 2025 that its 256 GB RDIMM built from 32 Gbit dies had completed Intel’s data center certification, and Micron samples a 256 GB 3DS RDIMM it rates at 11.1 W against 19.4 W for two 128 GB modules. The site ranks 24 GB, 48 GB, 96 GB and 256 GB modules alongside the binary sizes.

DDR5 dies

The same revision letters apply: SK hynix’s DDR5 decoder lists “Generation. M 1st”, so its first 16 Gbit chip, H5CG48MEBDX, is the M-die, and the 16 Gbit H5CG48AGBD is the A-die, made on its 1a node according to TechInsights. Enthusiasts have favored SK hynix’s M and A dies for high-speed kits; as with B-die, that is owners’ experience rather than any maker’s rating. The leading nodes changed quickly: Samsung began mass-producing 16 Gbit DDR5 on its 12nm-class process in May 2023, SK hynix announced the industry’s first 1c DDR5 on August 29, 2024, and Micron sampled DDR5 on its first EUV node, 1-gamma, in early 2025. China’s CXMT showed DDR5-8000 on 16 and 24 Gbit dies in November 2025.

Which processors take which DDR5

Intel’s desktop processors, from the memory tables in their datasheets, in MT/s. “1DPC” is a board with one slot per channel; on a board with two, one module per channel runs at the 2DPC “1 DIMM” figure:

AMD’s AM5 processors list two modules and four separately:

Four modules on AM5 cost a third of the speed, which is the strongest reason to buy two larger modules; how much RAM you need works through the capacity side. Servers, by platform:

The PowerEdge R760 is a typical DDR5 server: 32 slots and 8 TB.

PMIC, voltage and overclocking profiles

The module’s power chip runs from 5 V on desktop modules and 12 V on server ones. Micron’s DDR5 module datasheets give the client PMIC5100 “~10.6W of average output power capability” from the 5 V input, which Rambus’s PMIC5100 accepts from 4.25 to 5.5 V. “Locked” and “unlocked” PMIC are enthusiasts’ words for a real mechanism. Micron’s datasheet says the PMIC can be configured before its regulators are switched on, and that if it is then left in its secure mode “the device locks out the ability to change the contents of most registers”; a PMIC left in non-secure mode can still be reprogrammed while it runs. Micron does not say which mode overclocking kits need for the voltages in their XMP 3.0 or EXPO profiles, and no maker publishes which of its modules ship which way. Kingston’s FURY Beast DDR5 profiles run at 1.25, 1.35 and 1.4 V for 5,200 to 6,800 MT/s. XMP 3.0 holds up to five profiles, three set by the maker and two rewritable by the user; AMD’s EXPO is the AM5 equivalent. Both say running out of specification can void the processor’s warranty.

DDR5 in the market, and what comes next

TrendForce forecast in August 2023 that DDR5 would pass DDR4 as the mainstream in PCs in the second half of 2024, and by its September 2026 report module makers had made DDR5 “their primary product line in the second half” of 2025. Then the AI build-out took the wafers: TrendForce counted conventional DRAM contract prices up 45% to 50% in the fourth quarter of 2025 (February 26, 2026) and about 93% to 98% in the first quarter of 2026, and forecast another 10% to 15% for the fourth quarter of 2026. No DDR6 standard had been published by October 2026; JEDEC published LPDDR6, its phone and laptop sibling, on July 9, 2025.

Who makes the DRAM, and where

Three companies sell about seven-eighths of the world’s DRAM, and the chips on almost any module on this site came from one of them. TrendForce’s ranking for the second quarter of 2026, published September 7, 2026:

Source: TrendForce, 7 Sep 2026 (2Q26 DRAM revenue ranking). Figures as of September 7, 2026. Revenue share, not bits shipped, from TrendForce's ranking table. 'Everyone else' is Nanya at 1.7%, Winbond at 0.6%, PSMC at 0.07% and all others at 0.5%.

Show the figures

Samsung, SK hynix and Micron took 87.6% of DRAM revenue in the second quarter of 2026, and CXMT 9.5% (Share of worldwide DRAM revenue, percent, 2Q26)

Period	Share of DRAM revenue
Samsung	39.4
SK hynix	24.9
Micron	23.3
CXMT	9.5
Everyone else	2.9

The order at the top changed twice in two years. SK hynix passed Samsung in the first quarter of 2025 on the strength of its high-bandwidth memory for AI accelerators, the first quarter in which Samsung had not led since the early 1990s, and held first place for three quarters. Samsung took it back at the end of 2025, when contract prices for ordinary DRAM rose 45% to 50% in a quarter and then almost doubled again, because Samsung has the most ordinary DRAM to sell. Quarterly DRAM revenue went from $27.0 billion in the first quarter of 2025 to $154.7 billion in the second quarter of 2026, almost all of it price. The 2026 DRAM shortage is the home for why.

How twenty makers became three

In the mid-1990s about twenty companies made commodity DRAM. Much of Micron’s capacity is the surviving hardware of the ones that left:

• Micron bought Texas Instruments’ memory business in 1998 and Toshiba’s Dominion fab in Manassas, Virginia, in 2002; Manassas still makes Micron DRAM. It bought Elpida in 2013, after Japan’s last DRAM maker (NEC and Hitachi’s merged units, plus Mitsubishi’s) filed for bankruptcy in February 2012 with 448 billion yen of debt; Elpida’s Hiroshima fab is Micron’s Japanese plant. Micron then took full control of Rexchip in Taichung and, in December 2016, of Inotera in Taoyuan, so most of Micron’s DRAM now comes from Taiwan.
• Hynix, the name Hyundai Electronics took in 2001, grew out of its takeover of LG Semicon in 1999, under Korea’s post-crisis restructuring, and became SK hynix when SK Group bought it in 2012.
• Qimonda, carved out of Infineon (itself spun out of Siemens) in 2006, filed for insolvency in January 2009.

One newer company matters. CXMT in Hefei is China’s DRAM maker, built since 2016, listed on Shanghai’s STAR Market on July 27, 2026, and shipping DDR5 and LPDDR5 to global PC and server makers; Dutch export licensing, under US pressure, keeps EUV lithography out of its reach. And the nodes all three leaders run are called “10 nm class” (1x, 1y, 1z, then 1a, 1b, 1c, or alpha, beta, gamma at Micron), names that are not a comparable physical dimension. Samsung used EUV on five layers of its 14 nm DRAM in 2021; Micron held off until its 1-gamma node in 2025.

Wafers mostly in Korea and Taiwan, assembly across Asia

A DRAM wafer takes months to process. The dies are probed, repaired, cut, packaged and tested in a separate back-end plant, often in another country. SK hynix’s US prospectus of July 2026 lists wafer fabs in Icheon, Cheongju and Wuxi and assembly and test in Icheon, Cheongju and Chongqing; about 35% to 40% of its DRAM came from Wuxi in 2025, which since the end of 2025 needs an annual US license to receive American equipment. Micron’s fiscal 2026 annual report lists component and module assembly and test in Taiwan, Singapore, Malaysia, China and India, where its Sanand plant opened on February 28, 2026 and sent its first modules to Dell. New wafer capacity is slow: Micron’s first Idaho fab is due to ship wafers in mid-2027 and its New York fab in 2030, backed by up to $6.1 billion of CHIPS Act grants (up to $6.4 billion counting the Manassas upgrade).

Who builds the modules

The chipmakers build most server modules themselves and sell them to server makers and cloud operators. Retail upgrade and gaming modules mostly come from companies that buy chips and assemble them, and one of them is bigger than the rest put together. TrendForce’s ranking of 2025, published September 22, 2026, put third-party module revenue at $21.2 billion and Kingston’s share at 62%, then ADATA at about 6%, Ramaxel about 4%, Kimtigo, Team Group, Patriot, Innodisk, Apacer and AGI.

Crucial is gone as a retail brand. Micron announced on December 3, 2025 that it would leave the consumer business it had run since 1996, and shipped Crucial products through February 2026; used Crucial modules now come only from stock already in the world, and Micron keeps honoring the warranties. Micron still sells Micron-branded modules to business customers.

How DRAM and modules are tested

Wafer, repair, burn-in and package test

SK hynix’s April 2023 explainer of its own back end gives the order. On the wafer: electrical parameter monitoring of transistors and contacts, a wafer burn-in under heat and voltage to bring early-life defects forward, a probe test of every die through a probe card, and repair. Every DRAM die carries spare rows and columns; failing addresses found at probe are rerouted to spares, classically by blowing laser fuses, and the die is tested again. After packaging come a test during burn-in, then package tests at temperature corners at least 10% above the specified maximum and 10% below the minimum, speed tests that check each chip runs at its target speed, and a visual check for cracks and missing solder balls after laser marking, just before shipping. DDR4 and DDR5 add post-package repair, which lets a running system retire a failing row in the field.

The testers are specialized machines. Advantest’s T5503HS2 tests DDR5 at up to 9 Gbps on 16,256 channels; its T5835 tests 768 packaged devices at once; Teradyne’s Magnum 7H, launched August 2025, tests HBM stacks. FormFactor and Micronics Japan are among the leading makers of the probe cards that touch every die.

Module test

Once the chips are on a board, the module is tested again, and this is where a brand earns its name. Kingston says it tests 100% of its finished modules, “every cell on every chip on every module”, with two kinds of tester: automatic test equipment running stress patterns at speed, and real motherboards running operating systems and applications. It describes a guardband test at the four corners of voltage and temperature for each new design, more than 35 quality checkpoints, and for its server modules, since 2004, a patented “Dynamic Server Burn-In” that compresses three months of heavy use into 24 hours with temperature, voltage and workload controlled together.

Qualification: what “passed” means

JEDEC’s JESD47 sets the stress tests a new chip design must pass, on sample lots, before it ships at all. In the 2009 text, the high-temperature operating life test runs three lots of 77 devices for 1,000 hours at a junction temperature of at least 125 °C with zero failures allowed, and its own example works out that 1,000 hours at 125 °C equals about nine years at 55 °C. Temperature cycling runs 700 cycles from -55 to +125 °C, or an equivalent condition such as 850 cycles from -40 to +125 °C; the humidity test runs 1,000 hours at 85 °C and 85% humidity, or a shorter accelerated HAST. Soft errors from alpha particles and neutrons are measured under JESD89. Above that sit Intel’s and AMD’s platform lists, motherboard makers’ lists and the server makers’ own part numbers, each a separate test of the same module.

The grades a used buyer meets

Not every DRAM chip is sold fully tested. Makers sell eTT, “effectively tested”, parts that are statistically tested against the datasheet, and UTT, untested parts with a datasheet and no verification, leaving the testing to the module maker. In July 2005 an eTT 256 Mbit DDR-400 chip averaged $2.57 against $2.69 for a fully tested branded one. Micron also sells graded components through its SpecTek division, whose grades the chips themselves decodes. A chip with no maker’s logo, a module brand’s own logo or a blank top hides its origin, which is not proof of a fault but is a reason to read the SPD and test on arrival, as buying used RAM on eBay sets out.

The five generations on the used market

DDR (listings). 184-pin modules from machines of 2000 to about 2005, mostly DDR-400 and DDR-333 at 256 MB to 1 GB, and registered DDR from early Opteron servers and the Xeon servers of 2002 to 2005. Bought to keep an old machine alive rather than to build one. Examples: Samsung’s M368L3223FTN-CB3 desktop module and M312L5720CZ3-CCCQ0 registered one.

DDR2 (listings). The Core 2 and Athlon 64 X2 era and the first FB-DIMM servers: DDR2-800 desktop modules, DDR2-667 server modules, and FB-DIMMs, which fit only FB-DIMM machines. Typical: M378T2863QZS-CF7, a 1 GB DDR2-800 desktop module, and M393T5160QZA-CE6, 4 GB registered.

DDR3 (listings). The largest pool of cheap server memory: registered DDR3 from Xeon 5500 to E5 v2 machines, at 1333 and 1600 MT/s, much of it DDR3L at 1.35 V. Check whether a desktop board takes 1.35 V only before buying plain 1.5 V modules. Typical: Micron’s MT36JSF2G72PZ-1G9E1HF, 16 GB registered DDR3-1866 at 1.5 V.

DDR4 (listings). The generation retiring from data centers now, so registered DDR4 at 3200 and 2400 MT/s is plentiful; desktop and laptop modules stay in demand for machines people keep. Typical: Micron’s MTA36ASF8G72PZ-3G2, 64 GB registered, and SK hynix’s HMA81GU6AFR8N-UH, 8 GB desktop. Is DDR4 still worth buying prices it.

DDR5 (listings). Current, and still mostly new or nearly new: unbuffered desktop modules from 4800 to 6400 MT/s and beyond, registered modules from the first DDR5 servers, which cannot be used in an ordinary desktop board (Threadripper 7000 and 9000 and Xeon W workstations take them). Typical: Samsung’s M323R4GA3BB0-CQK, 32 GB unbuffered, and M321R8GA0BB0-CQK, 64 GB registered.

The Trends page follows the price of a gigabyte in each generation over time, and RAM prices compares them now.

Questions people ask about DDR4 and DDR5 modules

How many pins do DDR4 and DDR5 modules have?

Both desktop modules have 288 contacts at 0.85 mm, with the notch in different places; DDR5 modules rated 6,400 MT/s and above may have 287, contact 220 removed. Laptop modules have 260 contacts on DDR4 and 262 on DDR5, at 0.5 mm.

What voltage do DDR4 and DDR5 use?

DDR4 runs at 1.2 V with a 2.5 V word-line supply, both from the motherboard; XMP kits commonly run 1.35 V. DDR5 chips run at 1.1 V with a 1.8 V word-line supply, made on the module by its PMIC from 5 V (desktop, laptop) or 12 V (server).

Is DDR5 backward compatible with DDR4?

No. The notch, the power delivery and the protocol all differ, and no adapter exists. Intel’s 12th to 14th-generation processors support both, but nearly every board takes one or the other.

Can a DDR5 server module go in a desktop?

Not in an ordinary desktop board, though Threadripper 7000 and 9000 and Xeon W workstations take nothing else. DDR5 registered and unbuffered modules have different notches and take different input voltages, 12 V and 5 V, so the wrong one does not go in. On DDR4 they share a notch, so a server module seats in a desktop and the machine fails to start.

What do PC4-3200AA and PC5-4800B mean?

PC4-3200AA is DDR4 at 3,200 MT/s in bin AA, CL 22-22-22; the same module is often sold as PC4-25600, its bandwidth in MB/s. PC5-4800B is DDR5 at 4,800 MT/s in bin B, 40-39-39, sometimes sold as PC5-38400.

What is the biggest DDR4 or DDR5 module?

DDR4: 32 GB for desktops and laptops, 64 GB registered, 256 GB as a 3DS RDIMM. DDR5: 64 GB as an ordinary desktop UDIMM, 128 GB as a four-rank CQDIMM for Intel Z890 boards, and 256 GB for servers, in 2026.

Does DDR5 have ECC built in?

Every DDR5 chip corrects single-bit errors inside itself, but reports only an error count in its mode registers and does not protect the path to the processor. A module has real ECC only if it carries extra chips: 72 bits wide on an ECC UDIMM, usually 80 on an RDIMM. ECC against non-ECC covers the difference.

What is a CUDIMM?

A DDR5 desktop module with a clock driver on it, for 6,400 MT/s and above. Intel’s Core Ultra 200S uses the driver; AMD’s AM5 and other platforms whose firmware accepts the module run it with the driver bypassed at their normal speed once a BIOS update adds that mode, though MSI warns that support varies by AM5 processor.

What is B-die?

Samsung’s third revision of its 8 Gbit DDR4 chip, prized by overclockers, rated by Samsung to DDR4-3200 CL 22 at most (DDR4-2666 in its PC and server table) and listed for end of life in 2019. The B is the revision letter in the part number.

Is DDR4 discontinued?

Not entirely: in late 2026 Samsung and SK hynix are winding it down, Micron makes it only for automotive, industrial, medical, aerospace and defense customers, and Taiwan’s Nanya is expanding. Prices have risen, and per chip DDR4 now costs more than DDR5.

What a listing cannot tell you

A photograph shows the notch, the label and the chips; the part number decodes the rest. On most third-party modules, none of them shows which die revision is inside without the chip markings, whether the SPD still matches the label, which needs a reader in a running machine, how a module was run, since no DRAM keeps a record of its hours or its overclocks, or whether a DDR5 module’s PMIC is healthy, which shows only when it powers up. Read the label against the part number, count the chips against the organization, and test it inside the return window. The module will usually be what the label says, because the label, the SPD and the chips are three separate things to forge, and most sellers forge none of them.