DDR4 vs DDR5: which should you actually buy?

Buy whichever generation your motherboard takes: DDR4 and DDR5 are physically and electrically incompatible, no adapter is possible, and the memory controller inside the CPU speaks one generation only. Nobody really picks a memory generation; they pick a socket, and the socket picks the memory. If you are choosing a whole platform, choose DDR5, even at the two to two and a half times DDR4’s price per gigabyte that US retail trackers showed in early September 2026: its capacity ceiling is twice as high, its parallelism is real on anything with cores to spare, and DDR4’s supply is shrinking with nothing being built to relieve it. DDR4 is still the right buy on a board you already own, for a home server built from cheap registered ECC DDR4, and on a budget LGA1700 build, the one platform where the board rather than the processor decides.

Where a figure comes from a standard or a vendor, the document is named in the text; where it is worked out here, the arithmetic is shown. Prices on this site move daily, so this guide points to the page that shows the current figure rather than freezing one into prose. What 2026 prices mean for DDR4 in dollars and in frame rate is worked through in the DDR4 value guide.

Which to buy, by situation

Past the socket, what matters is how many modules, what capacity, what speed and what rank count, and those turn on facts about the silicon that no listing title carries.

Price against performance in 2026

Both rows are US retail from third-party price trackers rather than from this site, they disagree with each other on absolute levels, and they move daily. Read them for the ratio, which is the durable part:

• What the premium is. At the same 32 GB capacity, 409 / 179 = 2.28. Retail DDR5 sat between two and two and a half times retail DDR4 per gigabyte whichever tracker you opened.
• What it buys in games. On LGA1700, the one platform that takes both, Tom’s Hardware’s July 2026 retest and TechSpot’s December 2025 retest, both at 1080p on an RTX 5090, put DDR4’s loss at 9% to 17% in CPU-bound games. Tom’s paired a fast DDR5-7200 kit with DDR4-3200 in four 8 GB modules, and TechSpot paired DDR5-6000 with a premium DDR4-3600 CL14 kit, so neither is a like-for-like mainstream pairing and the range describes those benches, not every DDR4 build. The DDR4 value guide prices each point of that gap. Where the graphics card is the limit, memory-scaling results cluster inside a few percent whatever is in the slots.
• What it buys elsewhere. Little on one thread: a DDR5-6000 CL30 kit reaches its first word in the same 10.00 ns as a DDR4-3200 CL16 kit. Real gains on many cores touching unrelated memory, and the most on a machine with no graphics card.
• What it buys later. Twice the capacity ceiling, 128 GB in two slots at full speed against DDR4’s 64 GB, and a generation the DRAM makers are moving wafers to, where DDR4’s lines are being wound down.

To read the current premium, open DDR4 kits totaling 32 GB and DDR5 kits totaling 32 GB and compare the median price per gigabyte in each page’s summary line. Trends shows how this site’s own DDR4 and DDR5 prices per gigabyte have moved since October 3, 2026. Compare at the same capacity, never the cheapest rows, for the reasons in the price section.

Three checks before you buy, in order

1. Does the socket take it. The CPU’s memory controller decides, except on LGA1700, where the CPU takes both and the board decides permanently. Confirm with how to check what RAM fits or the CPU index before anything else, because nothing below this matters if it is wrong.
2. Will the arrangement downclock it. Count slots, not just modules: four populated slots costs an AM5 machine a third of its data rate, and two modules in a four-slot Intel board run slower than the same two in a two-slot one (see the derating table). Buy the capacity you want in two modules wherever the capacity ladder allows it, which on DDR5 now includes 48 GB and 64 GB modules and on DDR4 stops at 32 GB.
3. Does the grade need something your board can use. An XMP or EXPO profile a board cannot apply leaves the module at its JEDEC bin. A CUDIMM in a board without clock-driver support runs in bypass. A registered module in an unbuffered slot does not run at all.

Past those three, compare price per gigabyte at the capacity you want rather than at the capacity that happens to be cheapest, using the all-generations table and reading the median rather than the cheapest row.

The socket decides, and the one exception is a board, not a CPU

Both generations ship as 288-pin desktop DIMMs of the same length, and the only physical difference that matters is that the notch in the bottom edge has moved. That notch is the entire protection system, and it works: a DDR4 module will not seat in a DDR5 slot, and pressing harder bends the contacts in the slot rather than making it fit. On laptops you can count the difference: 260-pin DDR4 SODIMM against 262-pin DDR5 SODIMM, in packages of identical outline.

A passive adapter is not merely absent from the market but impossible, because everything behind the pins differs too. DDR4 takes 1.2 V VDD from the motherboard’s regulator and a 2.5 V VPP rail for the wordline boost; a DDR5 module takes 5 V on a desktop or laptop slot, or 12 V on a server slot, and makes its own 1.1 V VDD, 1.1 V VDDQ and 1.8 V VPP. DDR4 carries a command on a wide address bus in one clock cycle; DDR5 carries it on a narrower command and address bus over two cycles, per sub-channel, each sub-channel with its own chip select and clock. DDR5 receivers add decision feedback equalization and train their reference voltage on-die, and DDR5’s presence detect sits behind a hub on an I3C Basic bus rather than in an EEPROM on the board’s SMBus. An adapter that bridged all of that would be a memory controller, and it would be slower than the memory it was adapting.

So the socket settles the generation, with exactly one class of exception, and it is the one people get wrong. Intel’s LGA1700 processors - 12th, 13th and 14th generation Core - have a memory controller that can speak either generation. The CPU takes both. The board takes one, because the slots are soldered to it, and no board offers both slot types usable at once. On that platform the rule is “whichever your board has”, and swapping generations means a new board while keeping the CPU. Everywhere else there is nothing to decide: AM4 and LGA1200 are DDR4, AM5 and LGA1851 are DDR5.

A DDR4 LGA1700 board and a DDR5 LGA1700 board take the same CPU, and they do not cost the same to populate. On a second-hand 12th or 13th generation machine, the memory generation it happens to carry is a larger part of the upgrade cost than the processor inside it, so work out which one you are looking at before you price the upgrade. How to check what RAM fits is the procedure; the CPU index lists what each controller supports, and the server index does the same by machine model.

Two sub-channels per module, and why that was free

A DDR4 module presents one 64-bit data path. A DDR5 module presents two 32-bit paths that are addressed separately, each with its own command bus, chip select and clock, so they can work on different rows of different banks in the same instant. The module is not one device that got wider or faster. It is two half-width devices sharing a circuit board.

The gain is parallelism rather than throughput, which is most of what people get wrong about the generation. A controller’s problem is rarely raw bandwidth; it is that a request arriving while the bus is busy has to wait, and that a request for a row not already open pays the full activate penalty first. Two independent sub-channels halve the chance of a collision and double the rows that can be open at once. Where several cores pull from unrelated addresses - a compile, a video encode, half a dozen virtual machines, a database walking an index - that is where the generational gain lands. On one hot thread with a predictable stride it lands nowhere, which is most of the reason memory-scaling results in GPU-bound games cluster inside a few percent.

Halving the width of a data path ought to halve what one access moves, and it does not, because DDR5 doubled the burst length to 16 at the same time:

access granularity = bus width in bits x burst length / 8

DDR4    64 bits x  8 beats / 8 = 64 bytes
DDR5    32 bits x 16 beats / 8 = 64 bytes

Both generations move exactly one 64-byte cache line per access. That is the constraint, not a coincidence, so the split cost nothing in efficiency: the parallelism was obtained by changing the burst length, not by adding pins. The prefetch depth follows from the same arithmetic, because the DRAM array fetches a wide row internally and clocks it out narrow and fast:

DDR4-3200,  8n prefetch:  3200 MT/s / 8  = 400 M internal fetches/s
DDR5-6400, 16n prefetch:  6400 MT/s / 16 = 400 M internal fetches/s

A DDR5-6400 module’s DRAM array is running at the same 400 MHz as a DDR4-3200 module’s. The data rate doubled because the prefetch doubled, not because the cells got faster, and the cells have not been meaningfully faster since DDR2. The speed guide runs the same conversion from the other direction, starting at the MHz figure on the label.

DDR5 also doubled the bank groups: a x8 device has eight groups of four banks, thirty-two banks, against DDR4’s four groups of four (x16 devices get half of that in both generations). Accesses to different groups can go back to back at the short tCCD_S delay rather than the long tCCD_L, so more groups let one stream keep the bus fed. What did not change is the row cycle, which takes roughly the nanoseconds it took three generations ago; everything since DDR2 has hidden that latency behind more concurrency rather than reducing it.

One DDR5 module is not “dual channel”

A desktop CPU has two 64-bit memory channels. On DDR4 that is two modules. On DDR5 each 64-bit channel is presented as two 32-bit sub-channels, so the CPU has four sub-channels in total and one DDR5 module fills two of them. A single DDR5 stick gives you the same half of the controller’s width a single DDR4 stick did.

Motherboard manuals and reporting tools will cheerfully describe a single DDR5 module as running dual-channel. The module genuinely has two independent channels on it, but that is not the sense the phrase carried for the previous twenty years. Buy two modules on a desktop board, for exactly the reason you always did.

It matters most on a laptop or small-form-factor machine with two SODIMM slots and one populated at the factory, a very common second-hand configuration. Adding the second module is worth more than replacing the first with a larger one, up to the point where capacity starts forcing the machine to swap. DDR5 laptop modules and DDR4 laptop modules are listed separately here because a SODIMM listing title very often omits the generation.

Latency in nanoseconds has not moved since 2007

CAS latency is a count of clock cycles, not a duration. To compare it across generations, convert it with the length of a bus clock cycle, which is two divided by the data rate, because DDR transfers on both clock edges:

tCK (ns)    = 2000 / data rate in MT/s
CAS in ns   = CL x tCK

Worked across five generations, at a JEDEC grade and at a typical enthusiast grade for each. The CL values are the ordinary market grades, and every one can be checked against a module label:

Twenty-two years and five generations of standard took the time from a column command to the first byte from fifteen nanoseconds to about ten. A third, against a data rate that rose by a factor of twenty-two in the same period. Bandwidth scaled. Latency did not, and nothing in the DDR5 speed bins suggests it is about to.

So a premium for a low CAS number buys a gain that is real and small, while two modules instead of one, or not derating a channel by filling four slots, gains more and costs nothing. CL16 against CL22 at the same data rate is four nanoseconds; CL16 at 3200 against CL16 at 3600 is one nanosecond the other way. The latency guide covers timings in full. DDR3, DDR2 and the original DDR are still listed here, and their first-word latency is not far off a modern kit’s.

The first year of a generation is always the slow year

DDR5-4800 CL40 is 16.67 ns, sixty-seven percent worse than the 10.00 ns a good DDR4-3200 kit was already delivering on the day DDR5 launched. That is why the early DDR5 reviews were unenthusiastic, and why a lot of still-circulating advice says DDR5 is slower than DDR4. It was, and then it stopped being. A new standard launches at the highest data rate the process can yield in volume, with whatever cycle count first silicon needs, and as the process matures the achievable cycle count at a given data rate falls; that takes about two years. DDR4 did exactly this: DDR4-2133 CL15 at launch is 14.06 ns, worse than the DDR3-1866 CL9 kits on sale at the time.

Never compare a new generation’s launch bins against the outgoing generation’s mature bins, and never assume a review written in a generation’s first year still describes the parts on sale. DDR5 in 2026 is not DDR5 in 2021, and the modules in the DDR5 listings are not the modules those reviews measured.

CAS latency is not access latency

CAS latency applies only when the row you want is already open. For a closed row the activate comes first and costs tRCD; for a row conflict, where a different row in the same bank has to be put away first, you pay tRP on top:

row already open        latency = CL
row closed              latency = tRCD + CL
row conflict            latency = tRP + tRCD + CL

Worked on the two grades a buyer is most likely to be choosing between, using the primary timings printed on the kit:

DDR4-3200 CL16-18-18,  tCK = 0.625 ns
  row open      16 x 0.625                      = 10.00 ns
  row closed   (18 + 16) x 0.625                = 21.25 ns
  row conflict (18 + 18 + 16) x 0.625           = 32.50 ns

DDR5-6400 CL32-39-39,  tCK = 0.3125 ns
  row open      32 x 0.3125                     = 10.00 ns
  row closed   (39 + 32) x 0.3125               = 22.19 ns
  row conflict (39 + 39 + 32) x 0.3125          = 34.38 ns

Identical on the open-row case and slightly worse on both of the others. The generation did not make a single access faster. It made many simultaneous accesses cheaper, which is valuable on a machine with sixteen cores and worth nothing on one thread. A benchmark’s measured latency adds tens of nanoseconds of caches, interconnect and queueing on top, so these figures are for comparing two modules, where everything outside the DIMM cancels out.

A single core cannot use DDR5’s bandwidth

Peak bandwidth is eight bytes per transfer per 64-bit channel:

DDR4-3200   3200 x 8 =  25,600 MB/s   two modules   51.2 GB/s
DDR5-5600   5600 x 8 =  44,800 MB/s   two modules   89.6 GB/s
DDR5-6400   6400 x 8 =  51,200 MB/s   two modules  102.4 GB/s
DDR5-8800   8800 x 8 =  70,400 MB/s   two modules  140.8 GB/s

Those figures rarely show up anywhere a user can feel them, because a core has a fixed number of miss-handling registers (fill buffers) and stalls when they are all occupied. Single-core bandwidth is therefore a queueing result, and Little’s Law gives it:

bandwidth = outstanding requests x bytes per request / latency

N = 12 outstanding fills, 64-byte lines, 80 ns loaded latency
  12 x 64 / 80e-9  =  9.6 GB/s

N = 16 outstanding fills, same line size and latency
  16 x 64 / 80e-9  = 12.8 GB/s

Both inputs are assumptions at the right order for current desktop cores, ten to sixteen fill buffers and seventy to a hundred nanoseconds. Be generous with both and one core still lands around ten to fifteen gigabytes a second, between a tenth and an eighth of DDR5-6400’s 102.4 GB/s. It takes eight to ten cores hammering memory at once before the bus is what limits the machine.

That is the whole answer to “why did DDR5 not make my computer faster”. On one thread the bus was never the bottleneck, the latency was, and the latency did not improve. On sixteen threads touching unrelated memory the bus is the bottleneck, and the generation is worth what it costs. The third case is growing fast: an integrated GPU has no memory of its own, so on a machine with no graphics card, memory bandwidth is graphics bandwidth, and the DDR4 to DDR5 step is the largest single upgrade available to it. That is why handheld and small-form-factor machines moved to DDR5 and LPDDR5 faster than desktops did.

Four sticks cost more on DDR5 than they did on DDR4

Every rank on a channel is an electrical load, and past a point the only way to keep signaling reliable is to slow the bus down. On DDR4 that was mostly a server matter. On DDR5 it is in the desktop CPU’s published specification, and it is severe:

Intel’s table runs on slots per channel, then modules, then rank. AMD’s has no slot term and prints the same figure for both ranks: the specification field on a Ryzen 9 7950X reads 2x1R DDR5-5200, 2x2R DDR5-5200, 4x1R DDR5-3600, 4x2R DDR5-3600. Neither vendor charges you for the second rank on a single module, whatever the folklore says. Arrow Lake sits outside the table: Intel specifies Core Ultra 200S up to DDR5-6400, and it derates on four DIMMs like everything else. Your board manual carries the figure for your slot count, and that is the one to trust.

Both Intel rows derate for slots, not just for sticks. Two modules in a four-slot board run at 4400 where the same two in a two-slot board run at 4800 or 5600, because the empty slots are still stubs hanging off the bus, and a stub reflects. This is why two-slot ITX and small-form-factor boards often support higher memory speeds than full-size boards with four.

AM5 loses a third of its data rate going from two DIMMs to four. Four 16 GB modules instead of two 32 GB ones means DDR5-3600 rather than 5200 or 5600, for the same total capacity and usually a similar price, and the 32 GB module’s second rank costs nothing here. The four-stick configuration loses on every measure at once: lower data rate, more cycles for the same nanoseconds, more loads on the bus.

Board vendors validate well past these numbers, and most four-stick kits do better in practice; the table is what the CPU vendor will stand behind when a configuration is marginal. DDR4 derates too, but from a 3200 ceiling that four-slot desktop platforms were designed around. The penalty is a reason to buy DDR5 in two large modules. It is not a reason to buy DDR4.

Above the gear boundary, a faster kit can be slower

At DDR5 data rates the memory controller often runs at half the memory clock (Gear 2 on Intel, a two-to-one ratio on AMD), which adds a few nanoseconds that appear in no timing on the label. On AM5 the switch is explicit: there is a data rate above which the controller drops from one-to-one to two-to-one, and the latency penalty there can exceed the bandwidth gain. Above the point where your platform changes ratio, a faster kit can produce a slower machine, so find that boundary before paying for a higher bin. Gears, population and training are covered in the speed guide; on DDR4 the question rarely arose, because controllers kept up with 3200.

Where the JEDEC ladders stop

DDR4’s standard ends at DDR4-3200. There is no JEDEC DDR4-3600 or DDR4-4000 grade; those exist only as XMP profiles, and a board that cannot apply the profile runs the module at 3200 or below. DDR4-3200 is the top of the generation in any sense a standard recognizes, and DDR4-2666 is the grade most used server memory carries.

DDR5 launched in 2020 with the standard topping out at 6400, and later revisions extended it to 8800 MT/s; the current revision is JESD79-5D, published November 2025. The JEDEC ceiling describes the DRAM, not the memory controller: Arrow Lake stops at DDR5-6400 natively, and everything above that is an overclock whatever the kit is rated at. Three ceilings are routinely conflated, and almost every disappointed memory purchase is one mistaken for another:

Underneath all three sits the slot and rank count from the derating table.

CUDIMM, and the kit that quietly becomes a slower kit

From 6400 MT/s upward, client DDR5 modules carry a clock driver (JEDEC JESD82-531, used by CUDIMM and CSODIMM raw cards) that regenerates the clock on the module. It buffers the clock only, so a CUDIMM is still an unbuffered module for an ordinary desktop slot. In a board without native clock-driver support it runs in bypass mode, as a plain UDIMM. Intel’s Z890 platform takes the clock driver natively, which is how Core Ultra 200S reaches its specified DDR5-6400; AM5 has no equivalent, so a high-bin CUDIMM kit bought for an AM5 board is an ordinary UDIMM. It will post, and it will not do the thing you paid for, so check the board’s memory support list before paying the premium. DDR4 never needed a clock driver, because the problem it solves does not appear until roughly twice DDR4’s 3200 top grade.

Capacity: die, rank, module, channel

Module capacity is the product of four numbers, and with the formula you can tell from a listing title whether the module described can exist:

module capacity (GB) = die density (Gbit) x data devices per rank x ranks / 8

data devices per rank = data bus width in bits / device width in bits

The data bus is 64 bits on both generations, two 32-bit sub-channels on DDR5, and ECC devices are excluded because check bits are not user capacity. Device width is x4, x8 or x16 and is printed on the module label as part of the organization code: 2Rx8 means two ranks of x8 devices. The four cases that cover almost everything on this site, with the die densities JESD79-4 and JESD79-5 define:

DDR4 UDIMM, 16 Gbit x8, dual rank
  64 / 8 = 8 devices per rank
  16 x 8 x 2 / 8 = 32 GB                      the DDR4 unbuffered ceiling

DDR5 UDIMM, 32 Gbit x8, dual rank
  64 / 8 = 8 devices per rank
  32 x 8 x 2 / 8 = 64 GB                      the DDR5 unbuffered ceiling

DDR4 RDIMM, 16 Gbit x4, dual rank
  64 / 4 = 16 data devices per rank (+2 ECC)
  16 x 16 x 2 / 8 = 64 GB

DDR5 RDIMM, 32 Gbit x4, dual rank
  64 / 4 = 16 data devices per rank (+4 ECC)
  32 x 16 x 2 / 8 = 128 GB

Beyond that you need 3DS stacking: a 4-high stack of 16 Gbit DDR4 dies in a dual-rank x4 module gives 256 GB, and a 2-high stack of 32 Gbit DDR5 dies gives the same from half the stack height. Ranks and 3DS modules covers why the rank count matters as much as the capacity, and more on DDR5 because of the derating above.

Why DDR5 capacities stopped being powers of two

Every DDR4 die density is binary - 4, 8 and 16 Gbit - so every DDR4 module capacity is a power of two, as in every generation before it. DDR5 broke that with a 24 Gbit die, in volume production rather than a curiosity, and went past DDR4’s ceiling with a 32 Gbit one:

24 Gbit x8, single rank,  8 devices   ->  24 GB
24 Gbit x8, dual rank,   16 devices   ->  48 GB
24 Gbit x4, dual rank,   32 devices   ->  96 GB

Crucial’s CT64G56C46U5 proves the top of the DDR5 column: a 64 GB DDR5-5600 CL46 unbuffered DIMM, which Crucial lists as built from 32 Gbit devices. Sixteen of them, in two ranks, is the only arrangement that produces that number.

The 48 GB module is the interesting one, because DDR4 has no equivalent shape. Two of them make 96 GB in two slots at full speed; on DDR4, 96 GB means four sticks and the downclock, or a kit total written into a module field. That gives a parsing tell for any listing page: “96GB DDR4” in a title is always a kit total or an error, where on DDR5 it can be a single module. This site’s catalog treats the two generations differently for that reason, as the methodology page describes.

The ceilings

Per-channel and per-socket limits are set by the memory controller, and on a server they usually bind first; a machine’s published maximum is what the vendor validated rather than what the arithmetic allows. On a desktop:

Server memory capacity limits covers why a machine rated for a headline maximum often will not take it. Most desktop builds land on 16 GB, 32 GB or 64 GB DDR4 kit totals, and DDR5 has the same three rungs: 16 GB, 32 GB and 64 GB. How much a workload needs is in how much RAM you need.

On-die ECC is a yield measure, and it is not ECC

Every DDR5 die corrects single-bit errors internally, and it has no choice in the matter: JESD79-5 makes it mandatory. 128 data bits are stored alongside 8 check bits, a 136-bit codeword with single-error correction, decoded inside the die before anything reaches the module’s data pins. Eight is the smallest number of check bits that can correct one error in 128 data bits.

It exists because a DRAM cell is a capacitor that every generation makes smaller, with less margin between a stored one and a stored zero. By DDR5 densities, dies that would have been scrapped on a DDR4 process are shippable if the die repairs itself on the way out. DDR5 dies are not more reliable than DDR4 dies at the cell. They are less reliable at the cell, and corrected before you see it.

What on-die ECC hides from you

It protects the array and nothing else. From the data pins onward - the module’s traces, the connector, the motherboard and the CPU’s receiver - the data is unprotected, so a bit flipped by a marginal contact, a noisy rail or a badly trained interface is not covered. Protecting the bus takes extra DRAM devices on the module and a controller that reads them, which is what ECC means on a listing page; the ECC guide covers that and how to prove which one a running machine has.

It reports nothing. There is no machine check, no EDAC counter, no log line and no equivalent of a drive’s SMART fields. A DDR5 module can be quietly correcting at a high rate for months and present as perfectly healthy.

It breaks memory testing. If a marginal cell flips and the die corrects it before the pattern leaves the chip, the test passes. A DDR5 module can pass an overnight memtest run with cells that are already failing, right up until the failure rate exceeds one bit per codeword, when it starts producing hard, uncorrectable errors with no warning period in between. DDR4 gave you a degradation curve you could observe. DDR5 gives you a cliff. For a used buyer that is the most important practical difference, and it runs against the intuition that the generation with built-in error correction must be the safer second-hand purchase.

The same confusion produces a common listing error: “DDR5 with ECC” at a consumer price is describing on-die ECC, which every DDR5 module has. The tell is the data width: a x64 module is non-ECC whatever the title says, and real ECC is x72 on DDR4 or x80 on DDR5. In a photograph, an ECC DDR5 module built from x8 devices carries ten DRAM packages per rank, not eight.

Real ECC: 72 bits on DDR4, 80 on DDR5

A DDR4 ECC module is 72 bits, 64 data plus 8 check, a 12.5 percent overhead. Every DDR5 ECC module on the market is 80 bits, because each 32-bit sub-channel carries its own 8 check bits: a 25 percent overhead, double DDR4’s, which buys back the ability to survive a dead device. An ECC DDR5 module built from x4 devices has twenty per rank where the DDR4 equivalent had eighteen. The ECC guide works the arithmetic out in full. DDR5 dies can also scrub their own arrays and count what they corrected in their mode registers, which a DDR4 die does not do, but that count is not readable from a listing: the die knows its own health, and nothing between it and a buyer will surface it.

The power supply moved onto the stick

On DDR4 the motherboard regulates 1.2 V and feeds it to the slot, and the module has no active silicon besides the memory chips. On DDR5 the slot carries 5 V on a desktop or laptop board, or 12 V on a server board, and a power management IC (PMIC) on the module makes VDD at 1.1 V, VDDQ at 1.1 V and VPP at 1.8 V. The widely quoted 12 V figure belongs to RDIMMs and LRDIMMs; a desktop UDIMM takes 5 V, and mixing the two up is how people conclude their board is out of specification when it is not.

The currents explain why this has to be a switching regulator. Using a module power figure in the ordinary range for a mid-capacity desktop DIMM under load:

module drawing about 5 W, nearly all of it on the 1.1 V rails

  current on the 1.1 V rail   =  5 W / 1.1 V   =  4.5 A
  current drawn from 5 V in   =  5 W / 5 V     =  1.0 A, before conversion losses
  at 90 percent efficiency    =  1.1 A in, and 0.5 W dissipated on the module

Four and a half amps at 1.1 V, from a part the size of a grain of rice a centimeter from the DRAM it powers. Half a watt of conversion loss is now dissipated on the module rather than on the motherboard, which is a large part of why DDR5 modules run warmer than DDR4 modules of comparable capacity, and why the SPD hub was given a mandatory temperature sensor at the same time.

Locked and unlocked PMICs

JEDEC gives the PMIC a secure mode: once the module vendor has set the rail voltages, a secured PMIC refuses writes to most of its registers. The ceiling the module vendor chose is the ceiling you get, and no amount of firmware will move it. For a used enthusiast kit bought to tune, the PMIC is as much a part of the purchase as the DRAM die, and it is never in the listing title. It can change between revisions of one model number when a vendor switches PMIC supplier, so check the revision printed on the module label and treat a photograph of the label as a requirement; the part number index groups listings by that marking. On DDR4 the question does not exist, because the board’s VRM sets the voltage.

What a used DDR5 module can fail at that a DDR4 one cannot

Memory has no wear-out mechanism worth the name, which is why buying used RAM is one of the safest second-hand purchases in computing. DDR5 puts one real dent in that claim. A module now contains an active switching power stage, and those fail the way small switch-mode supplies fail, from heat, transients and component tolerances rather than from use. There is no visual tell: the module simply does not bring up its rails, and the board reports no memory present. It is not a common failure and should not put anybody off used DDR5, but used DDR4 does not have that category of risk at all.

The second consequence is a testing problem: you cannot test a DDR5 module without a DDR5 board, where a DDR4 stick can be checked in nearly anything with a slot. The compensating advantage: on a used DDR4 board, a degraded memory VRM produces exactly the symptoms of bad RAM and is hard to diagnose, because swapping the modules does not fix it. On DDR5 that failure moved onto a part you can replace for the price of a module.

Refresh, rowhammer, the SPD hub and overclocking profiles

Four more differences, each smaller for a buyer than the ones above.

Refresh got worse before it got better

DDR4 specifies a 64 ms retention window with 8192 refresh commands per window, one every 7.8125 us; DDR5 halved the window to 32 ms over the same 8192 commands, one every 3.9 us. Refresh commands arrive twice as often on DDR5, the same physics of smaller, leakier cells that made on-die ECC mandatory. JESD79-4 sets tRFC1, the time a device is unavailable per refresh, at 350 ns for an 8 Gbit DDR4 die, and JESD79-5 sets 295 ns for a 16 Gbit DDR5 die:

DDR4, 8 Gbit:    350 ns / 7812.5 ns  =  4.5 percent of all time
DDR5, 16 Gbit:   295 ns / 3900 ns    =  7.6 percent of all time

So a DDR5 die at twice the density spends two thirds more of its life refreshing, and that worsens as density rises. DDR5’s answer is same-bank refresh, which refreshes one bank in each of the eight bank groups and leaves twenty-four of thirty-two banks working, so a controller with a deep enough queue can schedule around it. DDR5 did not reduce the amount of refreshing. It made refreshing something the rest of the device can work around. Refresh timings are covered in the latency guide.

The same density makes rowhammer, where repeatedly activating one row flips bits in its neighbors, easier with every generation. DDR4’s defense, target row refresh, was proprietary, undocumented and broken repeatedly by published research; DDR5 put refresh management in the standard, with the controller counting activations and the device given time to protect the rows at risk. Published attacks exist against DDR5 too, and none of it is checkable on a used module: an improvement in kind rather than a guarantee.

The SPD hub, and why your DDR4 SPD reader does not work

Every module carries serial presence detect (SPD), a small memory holding its capacity, organization, timings and part number, which firmware reads at power-on. On DDR4 it is a plain EEPROM on the motherboard’s SMBus, which is why a cheap USB SPD reader works and decode-dimms can dump a module’s identity on almost any machine. DDR5 replaced it with a hub on an I3C Basic bus, with a mandatory temperature sensor alongside, so a DDR4 SPD reader does not work on DDR5 modules. On Linux the spd5118 hwmon driver reports each DDR5 module’s temperature in sensors and exposes its SPD contents as an eeprom attribute, so a DDR5 module in a running machine is far more inspectable than a DDR4 one: its label data, timings and temperature, though still not its health. How SPD and memory training decide the speed a module boots at is in the speed guide.

XMP 3.0 and EXPO

Both are non-JEDEC overclocking profiles stored in the SPD, and a board that cannot apply the profile still posts at the JEDEC bin, so a kit bought for the wrong platform is disappointing rather than dead. DDR4 has only XMP 2.0, with two profiles. XMP 3.0 carries five, three from the vendor and two rewritable by the user, and adds on-module voltage control, possible only because the PMIC moved onto the module. EXPO is AMD’s, DDR5 only and royalty-free, and is tuned around the controller ratios AM5 cares about. Most AM5 boards will read an XMP profile too, and when one fails it fails as a training failure at boot, so finding out is cheap. Both CPU vendors call running either profile overclocking. Profiles in detail are in the speed guide.

Server modules: registered DDR4 is cheap for a reason

Server memory buffers the command and address bus, the hard part of driving many ranks. A registered DIMM puts a registering clock driver between the connector and the DRAM (JEDEC JESD82-31 for DDR4, JESD82-511 for DDR5, where it has to drive two independent sub-channels from one package), and a load-reduced DIMM buffers the data path too. A registered module will not work in an unbuffered slot, and an unbuffered module will not work in a board that requires registered; registered vs unbuffered covers reading the label. The single largest source of returned memory on the used market is a server RDIMM bought for a desktop because it was cheap per gigabyte.

It is cheap for a good reason. Registered ECC DDR4 comes almost entirely from decommissioned data-center hardware, in volumes far beyond the demand for it, which gives it the lowest price per gigabyte of any current generation on this site. DDR5 servers are still in service, so registered DDR5 is scarce and expensive. That will reverse on data-center refresh cycles, but if you are building a home server in 2026, the DDR4 platform is the cheaper one by a wide margin and will remain so for several years. Check what your machine takes on the compatibility index - Dell’s range, for example - before assuming a cheap RDIMM is a bargain.

Laptops: 262 pins, and the form factor that replaces them

The physical difference is two pins, 260 against 262, in packages of the same outline with the notch in a different place. A DDR4 SODIMM and a DDR5 SODIMM are indistinguishable in a photograph taken from the wrong angle, which makes generation the single most common listing error in laptop memory. Do not buy one from a title. Read the label, or the part number, which encodes the generation unambiguously.

Many modern laptops have no slots at all: the memory is soldered, and increasingly it is LPDDR, a different standard that is not interchangeable with DDR5 in any form. For machines that keep sockets, JEDEC has standardized a compression-attached module that lies flat and is held by screws, because the SODIMM connector runs out at DDR5 speeds. It is compatible with nothing else, and there is essentially no second-hand market for it yet.

Identify the machine first and the memory second, never the reverse. How to check what RAM fits is the procedure, and DDR4 SODIMMs and DDR5 SODIMMs are listed separately here so that a search cannot silently cross generations.

What it costs per gigabyte, and why the crossover happened when it did

DDR5 costs much more per gigabyte than DDR4 at retail, as the price table shows, and yet the DRAM inside it is cheaper to make. Retail prices reflect inventory bought months ago; spot chip prices reflect what a module costs to build this week. At the chip level the ordering reverses: a 16 Gbit DDR4 die has cost more on the spot market than a 16 Gbit DDR5 die through 2026. No per-chip figure is printed here, because the trade trackers’ contract and spot series disagree with each other by more than the gap, but the sign and rough size hold: the older die at a clear premium, while the module built from it sells for less than half as much.

The three large DRAM suppliers have moved wafer starts to DDR5, LPDDR5X and high-bandwidth memory and are winding DDR4 lines down, so the older, technically inferior product becomes the more expensive silicon, and stays that way until the demand finally goes. Both generations rose steeply through the middle of 2026 and DDR5 rose further, so DDR4’s retail advantage widened while the chip cost underneath went the other way. That is the single best argument for not committing to a DDR4 platform in 2026 if you have a choice. Why prices rose is in the 2026 DRAM shortage, and whether to buy now or later is in buy RAM now or wait.

Checking it yourself, which is the only figure that stays right

price per gigabyte = listing price / total gigabytes in the listing
crossover ratio    = DDR5 per GB / DDR4 per GB, AT THE SAME CAPACITY

409 / 179 = 2.28x     both kits are 32 GB, so this is a clean ratio
                      the ratio, not the absolute price, is the decision

Every table on this site sorts by price per gigabyte by default, and the all-generations table is the only view where DDR4 and DDR5 modules sort against each other. The summary line at the top of any listing page gives the cheapest Buy It Now price per gigabyte and the median for that page, and Trends keeps the same measure over time.

Compare medians, or compare at a fixed capacity, and never compare the cheapest rows. The cheapest row on the DDR4 page is usually a small, old server module that nobody choosing between generations would consider, and the DDR5 page has no equivalent, because DDR5 has not been on the market long enough to have a bargain bin. Only a ratio at a fixed capacity, such as DDR4 kits totaling 32 GB against DDR5 kits totaling 32 GB, answers a buying question.

A bid is not a price. This site leaves bid-only auctions out of every table by default; ?bids=show brings them back, marked as bids. To drop auctions that also offer Buy It Now, add ?auctions=no while you work out what a configuration costs.

A kit total is not a module. “64GB (2x32GB)” is two modules, and the per-gigabyte figure is correct. “64GB” against a module part number that cannot be 64 GB is a listing error, and the capacity formula catches it before you pay.

The cheapest gigabyte tracked anywhere on this site is usually DDR3 registered ECC rather than anything current. That is what the end of a generation’s life looks like from the buyer’s side, and it is where DDR4 is heading over the next several years.

Buying either one used

Memory is one of the safest used purchases in computing, and that has not changed. The risks differ by generation.

DDR4 used risk is almost entirely authenticity and handling: relabeled modules, mismatched sticks sold as a matched kit, bent or corroded contacts, and modules pulled from machines whose real fault was not the memory. All of it is inspectable from photographs and the label, and a DDR4 module that posts and passes a memory test is essentially certain to keep working.

DDR5 used risk adds the PMIC and subtracts the diagnostic. The power stage can fail on its own, you cannot test the module without a DDR5 board, and the die may be correcting errors a test can never see. Put in the negative: a clean memtest pass is weaker evidence on DDR5 than it is on DDR4.

For both, buying used RAM on eBay covers the checks: read the label rather than the title, insist on a photograph of it, check that the organization code matches the claimed capacity using the formula above, and treat a seller who will not photograph a label as having answered the question. The part number index is the fastest route from a label marking to the module.

When DDR4 is still the right buy

You already have a DDR4 board. This is not a judgment call. Changing generation means a CPU, a board and the memory, and the memory is the cheapest of the three. Spend the difference on capacity: 64 GB of DDR4 beats 32 GB of DDR5 at anything that would otherwise touch swap, and the bandwidth arithmetic shows why the raw speed difference will not repay a platform change on a machine that is not bandwidth-bound.

A server or workstation refresh. Registered ECC DDR4 is the cheapest current-platform memory per gigabyte by a wide margin, and every DDR4 server retired adds to the pool. Check the buffering and the rank support first, per registered vs unbuffered and server memory capacity limits.

Budget LGA1700 builds. 12th to 14th generation Intel take either, decided by the board, and a DDR4 board with DDR4-3200 is still a coherent build at a considerably lower total price.

The exception across all three is the thing that changed this year: new DDR4 is a shrinking pool. If you expect to add capacity later, it will be more expensive and scarcer then, and eventually second-hand only. Fill the slots now rather than leaving room - advice that applies to DDR4 and emphatically not to DDR5, where leaving two slots empty is what keeps the channel at full speed. What DDR4 costs against DDR5 in 2026, in dollars and in frame rate, is in the DDR4 value guide.

What cannot be known from a listing

• Whether a DDR5 module’s PMIC is locked. It is not in the SPD or the title, it varies between revisions of the same part number, and the only reliable route is the module’s own label plus a vendor revision list.
• Whether a DDR5 die is correcting errors. A module one bit from uncorrectable presents identically to a new one.
• Which DRAM die is inside a given kit. Vendors change die suppliers within a part number without announcing it, so two kits of one model bought a year apart can behave differently.
• What speed a configuration will actually run at. The CPU’s published figure is a floor board vendors routinely beat and a ceiling some boards do not reach.
• Whether a used module was ever run outside specification. Memory keeps no counter, hours field or wear indicator, which is the good news and the bad news in one sentence.
• Whether a kit is matched. Two modules sold together were not necessarily binned together, and “matched pair” in a title means only that the seller wrote it.

Where this site’s catalog cannot source a field, it records it as not stated rather than inferring it, for the reasons on the methodology page: a speed or a capacity guessed from a title would put a module at the top of a price-per-gigabyte table on the strength of a typo.